Datasheet

DAC7565
www.ti.com SBAS412B –FEBRUARY 2008–REVISED MARCH 2011
SERIAL INTERFACE falling edge of SCLK is received, the SYNC line may
be kept LOW or brought HIGH. In either case, the
The DAC7565 has a 3-wire serial interface (SYNC,
minimum delay time from the 24th falling SCLK edge
SCLK, and D
IN
) compatible with SPI, QSPI, and
to the next falling SYNC edge must be met in order to
Microwire interface standards, as well as most DSPs.
properly begin the next cycle. To assure the lowest
See the Serial Write Operation timing diagram for an
power consumption of the device, care should be
example of a typical write sequence.
taken that the levels are as close to each rail as
possible. Refer to the Typical Characteristics section
The DAC7565 input shift register is 24 bits wide,
for Figure 36, Figure 57, and Figure 79 (Supply
consisting of eight control bits (DB23 to DB16) and 12
Current vs Logic Input Voltage).
data bits (DB15 to DB4). Bits DB0, DB1, DB2, and
DB3 are ignored by the DAC and should be treated
as don't care bits. All 24 bits of data are loaded into IOV
DD
AND VOLTAGE TRANSLATORS
the DAC under the control of the serial clock input,
The IOV
DD
pin powers the digital input structures of
SCLK. DB23 (MSB) is the first bit that is loaded into
the DAC7565. For single-supply operation, it can be
the DAC shift register, and is followed by the rest of
tied to AV
DD
. For dual-supply operation, the IOV
DD
pin
the 24-bit word pattern, left-aligned. This
provides interface flexibility with various CMOS logic
configuration means that the first 24 bits of data are
families and should be connected to the logic supply
latched into the shift register and any further clocking
of the system. Analog circuits and internal logic of the
of data is ignored. The DAC7565 receives all 24 bits
DAC7565 use AV
DD
as the supply voltage. The
of data and decodes the first eight bits in order to
external logic high inputs translate to AV
DD
by level
determine the DAC operating/control mode. The 12
shifters. These level shifters use the IOV
DD
voltage as
bits of data that follow are decoded by the DAC to
a reference to shift the incoming logic HIGH levels to
determine the equivalent analog output, while the last
AV
DD
. IOV
DD
is ensured to operate from 2.7V to 5.5V
four bits (DB3, DB2, DB1, and DB0) are ignored. The
regardless of the AV
DD
voltage, assuring compatibility
data format is straight binary with all '0's
with various logic families. Although specified down to
corresponding to 0V output and all '1's corresponding
2.7V, IOV
DD
operates at as low as 1.8V with
to full-scale output (that is, V
REF
– 1 LSB); see the
degraded timing and temperature performance. For
Data Format section for more details.. For all
lowest power consumption, logic V
IH
levels should be
documentation purposes, the data format and
as close as possible to IOV
DD
, and logic V
IL
levels
representation used here is a true 12-bit pattern (that
should be as close as possible to GND voltages.
is, 0FFFh for full-scale), even if the usable 12 bits of
data are extracted from a left-justified, 16-bit data
ASYNCHRONOUS RESET
format that the DAC7565 requires.
The DAC7565 output is asynchronously set to
The write sequence begins by bringing the SYNC line
zero-scale voltage or mid-scale voltage (depending
low. Data from the D
IN
line are clocked into the 24-bit
on RSTSEL) immediately after the RST pin is brought
shift register on each falling edge of SCLK. The serial
low. The RST signal resets all internal registers, and
clock frequency can be as high as 50MHz, making
therefore, behaves like the Power-On Reset. The
the DAC7565 compatible with high-speed DSPs. On
RST pin must be brought back to high before a write
the 24th falling edge of the serial clock, the last data
sequence starts. If the RSTSEL pin is high, the RST
bit is clocked into the shift register and the shift
signal going low resets all outputs to mid-scale. If the
register locks. Further clocking does not change the
RSTSEL pin is low, the RST signal going low resets
shift register data. After 24 bits are locked into the
all outputs to zero-scale. RSTSEL should be set at
shift register, the eight MSBs are used as control bits
power-up.
and the following 12 LSBs are used as data. After
receiving the 24th falling clock edge, the DAC7565
INPUT SHIFT REGISTER
decodes the eight control bits and 12 data bits to
perform the required function, without waiting for a
The input shift register (SR) of the DAC7565 is 24
SYNC rising edge. A new write sequence starts at the
bits wide, as shown in Table 5, and consists of eight
next falling edge of SYNC. A rising edge of SYNC
control bits (DB23 to DB16), 12 data bits (DB15 to
before the 24-bit sequence is complete resets the SPI
DB4), and four don't care bits. DB23 and DB22
interface; no data transfer occurs. After the 24th
should always be '0'.
Table 5. Data Input Register Format
DB23 DB12
0 0 LD1 LD0 0 DAC Select 1 DAC Select 0 PD0 D11 D10 D9 D8
DB11 DB0
D7 D6 D5 D4 D3 D2 D1 D0 X X X X
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