Datasheet

SYNC
SCLK
D
IN
Microwireä
CS
SK
SO
DAC7564
(1)
NOTE:(1)Additionalpinsomittedforclarity.
PC7
SCK
MOSI
SYNC
DAC7564
(1)
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
68HC11
(1)
P3.3
TXD
RXD
SYNC
DAC7564
(1)
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
80C51/80L51
(1)
DAC7564
www.ti.com SBAS413B –FEBRUARY 2008–REVISED MAY 2011
DAC7564 to Microwire Interface
MICROPROCESSOR INTERFACING
Figure 102 shows an interface between the DAC7564
DAC SPI Interfacing
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
Care must be taken with the digital control signals
are clocked into the DAC7564 on the rising edge of
that are applied directly to the DAC, especially with
the SK signal.
the SYNC pin. The SYNC pin must not be toggled
without having a full SCLK pulse in between. If this
condition is violated, the SPI interface locks up in an
erroneous state, causing the DAC to behave
incorrectly and have errors. The DAC can be
recovered from this faulty state by writing a valid SPI
command or using the SYNC pin correctly;
communication will then be restored. Avoid glitches
and transients on the SYNC line to ensure proper
operation.
Figure 102. DAC7564 to Microwire Interface
DAC7564 to an 8051 Interface
Figure 101 shows a serial interface between the
DAC7564 to 68HC11 Interface
DAC7564 and a typical 8051-type microcontroller.
Figure 103 shows a serial interface between the
The setup for the interface is as follows: TXD of the
DAC7564 and the 68HC11 microcontroller. SCK of
8051 drives SCLK of the DAC7564, while RXD drives
the 68HC11 drives the SCLK of the DAC7564, while
the serial data line of the device. The SYNC signal is
the MOSI output drives the serial data line of the
derived from a bit-programmable pin on the port of
DAC. The SYNC signal derives from a port line
the 8051; in this case, port line P3.3 is used. When
(PC7), similar to the 8051 diagram.
data are to be transmitted to the DAC7564, P3.3 is
taken low. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted; then, a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken high following the
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC7564 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore
Figure 103. DAC7564 to 68HC11 Interface
take this requirement into account, and mirror the
data as needed.
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC7564, PC7 is left low after the first eight bits are
Figure 101. DAC7564 to 80C51/80L51 Interface
transferred; then, a second and third serial write
operation are performed to the DAC. PC7 is taken
high at the end of this procedure.
Copyright © 2008–2011, Texas Instruments Incorporated 39