Datasheet

CLK
SYNC
D
IN
ValidWriteSequence:
Output/ModeUpdates onthe24thFallingEdge
24thFallingEdge 24thFallingEdge
DB23 DB0 DB23 DB0
Invalid/InterruptedWriteSequence:
Output/ModeDoesNotUpdate onthe24thFallingEdge
DAC7564
www.ti.com SBAS413B –FEBRUARY 2008–REVISED MAY 2011
SYNC INTERRUPT LDAC FUNCTIONALITY
In a normal write sequence, the SYNC line stays low The DAC7564 offers both a software and hardware
for at least 24 falling edges of SCLK and the simultaneous update function. The DAC
addressed DAC register updates on the 24th falling double-buffered architecture has been designed so
edge. However, if SYNC is brought high before the that new data can be entered for each DAC without
24th falling edge, it acts as an interrupt to the write disturbing the analog outputs.
sequence; the shift register resets and the write
DAC7564 data updates are synchronized with the
sequence is discarded. Neither an update of the data
falling edge of the 24th SCLK cycle, which follows a
buffer contents, DAC register contents, nor a change
falling edge of SYNC. For such synchronous updates,
in the operating mode occurs (as shown in
the LDAC pin is not required and it must be
Figure 95).
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
POWER-ON RESET TO ZERO-SCALE
asynchronous DAC updates. To do an LDAC
operation, single-channel store(s) should be done
The DAC7564 contains a power-on reset circuit that
(loading DAC buffers) by setting LD0 and LD1 to '0'.
controls the output voltage during power-up. On
Multiple single-channel updates can be done in order
power-up, the DAC registers are filled with zeros and
to set different channel buffers to desired values and
the output voltages are set to zero-scale; they remain
then make a rising edge on LDAC. Data buffers of all
that way until a valid write sequence and load
channels must be loaded with desired data before an
command are made to the respective DAC channel.
LDAC rising edge. After a low-to-high LDAC
The power-on reset is useful in applications where it
transition, all DACs are simultaneously updated with
is important to know the state of the output of each
the contents of the corresponding data buffers. If the
DAC while the device is in the process of powering
contents of a data buffer are not changed by the
up. No device pin should be brought high before
serial interface, the corresponding DAC output
power is applied to the device. The internal reference
remains unchanged after the LDAC trigger.
is powered on by default and remains that way until a
valid reference-change command is executed.
ENABLE PIN
No device pin should be brought high before power is
applied to the device. The internal reference is For normal operation, the enable pin must be driven
powered on by default and remains that way until a to a logic low. If the enable pin is driven high, the
valid reference-change command is executed. DAC7564 stops listening to the serial port. However,
SCLK, SYNC, and D
IN
must not be kept floating, but
must be at some logic level. This feature can be
useful for applications that share the same serial port.
Figure 95. SYNC Interrupt Facility
Copyright © 2008–2011, Texas Instruments Incorporated 31