Datasheet

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IOVDD and Level Shifters
INTEGRAL AND DIFFERENTIAL LINEARITY
GLITCH ENERGY
Daisy-Chain Operation
CHANNEL-TO-CHANNEL CROSSTALK
DAC7558
SLAS435A – MAY 2005 – REVISED DECEMBER 2005
falling-edge setup time, t4. After SYNC goes low, edges are received (following a falling SYNC), the
serial data is shifted into the device's input shift data stream becomes complete, and SYNC can be
register on the falling edges of SCLK for 24 clock brought high to update n devices simultaneously.
pulses. Any data and clock pulses after the SDO operation is specified at a maximum SCLK
twenty-fourth falling edge of SCLK are ignored. No speed of 10 MHz.
further serial data transfer occurs until SYNC is taken
Daisy-chain operation is also possible between
high and low again.
octal-channel DAC7558, dual-channel DAC7552, and
SYNC may be taken high after the falling edge of the single-channel DAC7551 devices. Dasy chaining
twenty-fourth SCLK pulse, observing the minimum enables communication with any number of DAC
SCLK Loop falling-edge to SYNC rising-edge time, t7. channels using a single serial interface. As long as
the correct number of bits are shifted using a
After the end of serial data transfer, data is
daisy-chain setting, a rising edge of SYNC properly
automatically transferred from the input shift register
updates all chips in the system. Following a rising
to the input register of the selected DAC. If SYNC is
edge of SYNC, all devices on the daisy chain
taken high before the twenty-fourth falling edge of
respond according to the control bits they receive.
SCLK, the data transfer is aborted and the DAC input
registers are not updated.
When DCEN is low, the SDO pin is brought to a Hi-Z
The DAC7558 can be used with different logic
state. The first 24 data bits that follow the falling edge
families that require a wide range of supply voltages
of SYNC are stored in the shift register. The rising
(from 1.8 V to 5.5 V). To enable this useful feature,
edge of SYNC that follows the 24th data bit updates
the IOVDD pin must be connected to the logic supply
the DAC(s). If SYNC is brought high before the 24th
voltage of the system. All DAC7558 digital input and
data bit, no action occurs.
output pins are equipped with level-shifter circuits.
Level shifters at the input pins ensure that external
In daisy-chain mode (DCEN = 1) the DAC7558
logic high voltages are translated to the internal logic
requires a falling SCLK edge after the rising SYNC, in
high voltage, with no additional power dissipation.
order to initialize the serial interface for the next
Similarly, the level shifter for the SDO pin translates
update.
the internal logic high voltage (AVDD) to the external
When DCEN is high, data can continuously be shifted
logic high level (IOVDD). For single supply operation,
into the shift register, enabling the daisy-chain
the IOVDD pin can be tied to the AVDD pin.
operation. The SDO pin becomes active and outputs
SDIN data with 24 clock-cycle delay. A rising edge of
SYNC loads the shift register data into the DAC(s).
The loaded data consists of the last 24 data bits The DAC7558 uses precision thin-film resistors
received into the shift register before the rising edge providing exceptional linearity and monotonicity.
of SYNC. Integral linearity error is typically within (+/-) 0.35
LSBs, and differential linearity error is typically within
If daisy-chain operation is not needed, DCEN should
(+/-) 0.08 LSBs.
permanently be tied to a logic-low voltage.
The DAC7558 uses a proprietary architecture that
When the DCEN pin is brought high, daisy chaining is
minimizes glitch energy. The code-to-code glitches
enabled. Serial data output (SDO) pin is provided to
are so low, they are usually buried within the
daisy-chain multiple DAC7558 devices in a system.
wide-band noise and cannot be easily detected. The
As long as SYNC is high or DCEN is low the SDO pin
DAC7558 glitch is typically well under 0.1 nV-s. Such
is in a high-impedance state. When SYNC is brought
low glitch energy provides more than 10X
low the output of the internal shift register is tied to
improvement over industry alternatives.
the SDO pin. As long as SYNC is low and DCEN is
high, SDO duplicates the SDIN signal with 24-cycle
delay. To support multiple devices in a daisy-chain,
SCLK and SYNC signals are shared across all
The DAC7558 architecture is designed to minimize
devices and SDO of one DAC7558 should be tied to
channel-to-channel crosstalk. The voltage change in
the SDIN of the next DAC7558. For n devices in such
one channel does not affect the voltage output in
a daisy chain, 24 n SCLK cycles are required to shift
another channel. The DC crosstalk is in the order of a
the entire input data stream. After 24 n SCLK falling
few microvolts. AC crosstalk is also less than –100
dBs. This provides orders of magnitude improvement
over certain competing architectures.
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