Datasheet

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Power Down
Input Data Format Selection
SERIAL INTERFACE
24-Bit Word and Input Shift Register
Asynchronous Clear
DAC7558
SLAS435A – MAY 2005 – REVISED DECEMBER 2005
brought low. The RST signal resets all internal
registers, and therefore behaves like the Power-On
The DAC7558 has a flexible power-down capability
Reset. The DAC7558 updates at the first rising edge
as described in Table 2 and Table 3 . Individual
of the SYNC signal that occurs after the RST pin is
channels can be powered down separately, or
brought back to high.
multiple channels can be powered down
simultaneously. During a power-down condition, the
If the RSTSEL pin is high, RST signal going low
user has flexibility to select the output impedance of
resets all outputs to midscale. If the RSTSEL pin is
each channel. If the PD pin is brought low, then all
low, RST signal going low resets all outputs to
channels can simultaneously be powered down, with
zero-scale.
the output at high impedance state (High-Z).
The DAC7558 has DB16 as a power-down flag. If this
flag is set, then DB11 and DB10 select one of the
DAC7558 can use unsigned binary (USB) or binary
three power-down modes of the device as described
twos complement (BTC) input data formats. Format
in Table 2 .
selection is done by the RSTSEL pin. If the RSTSEL
is kept low, the 12-bit input data is assumed to have
Table 2. DAC7558 Power-Down Modes
USB format, and any asynchronous clear operation
generates zero-scale outputs. If the RSTSEL pin is
DB11 DB10 OPERATING MODE
kept high, the 12-bit input data is assumed to have
0 0 PWD Hi-Z
BTC format and any asynchronous clear operation
0 1 PWD 1 k Ω
generates mid-scale outputs.
1 0 PWD 100 k Ω
1 1 PWD Hi-Z
The DAC7558 is controlled over a versatile 3-wire
The DAC7558 can also be powered down using the
serial interface, which operates at clock rates up to
PD pin. When the PD pins is brought low, all
50 MHz and is compatible with SPI, QSPI, Microwire,
channels simultaneously power down and all outputs
and DSP interface standards.
become high impedance. When the PD pin is brought
high, the device resumes its state before the power
down condition.
The input shift register is 24 bits wide. DAC data is
The DAC7558 also has an option to power down
loaded into the device as a 24-bit word under the
individual channels, or multiple channels
control of a serial clock input, SCLK, as shown in the
simultaneously selected by DB20. If DB20 = 0, then
Figure 1 timing diagram. The 24-bit word, illustrated
the user can power down the selected individual
in Table 1 , consists of 8 control bits, followed by 12
channels. If DB20 = 1, then the user can power down
data bits and 4 don't care bits. Data format is straight
the multiple channels simultaneously as explained in
binary (RSTSEL pin = 0) or binary twos complement
Table 3 . Power-down mode is selected by DB11 and
(RSTSEL = 1), where the most significant DAC data
DB10.
bit is DB15. Data is loaded MSB first (DB23) where
the first two bits (DB23 and DB22) should be set to
Table 3. DAC7558 Power-Down Modes for Multiple
zero for DAC7558 to work. The DAC7558 does not
Channels
respond to any other combination other than 00.
DB19 DB18 DB17 OPERATING MODE
DB21 and DB20 (LD1 and LD0) determine if the input
0 0 0 PWD Channel A-B
register, DAC register, or both are updated with shift
register input data. DB19, DB18, and DB17 (SEL2,
0 0 1 PWD Channel A-C
SEL1, and SEL0) bits select the desired DAC(s).
0 1 0 PWD Channel A-D
DB16 is the power-down bit. If DB16 = 0, then it is a
0 1 1 PWD Channel A-E
normal operation, if DB16 = 1, then DB11 and DB10
1 0 0 PWD Channel A-F
determine the power-down mode (Hi-Z, 1 k Ω , or 100
1 0 1 PWD Channel A-G
k Ω ). DB20 bit also gives the user the option of
powering down either a single channel or multiple
1 1 0 PWD Channel A-H
channels at the same time. See Power Down section
1 1 1 PWD Channel A-H
for more details.
The SYNC input is a level-triggered input that acts as
a frame-synchronization signal and chip enable. Data
The DAC7558 output is asynchronously set to
can only be transferred into the device while SYNC is
zero-scale voltage immediately after the RST pin is
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC-to-SCLK
20