Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VQFN 32

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

Input

DAC

String

DAC A

String

DAC H

Interface

Logic

Power-On

Reset

Power-Down

Logic

IOV

VREF2

SCLK

SYNC

SDIN

OUT

SDO

RST RSTSEL AGND DGND VREF3 VREF4 PD

−

VFBA

−

VFBH

VREF1V

DCEN

DAC7558

SLAS435A – MAY 2005 – REVISED DECEMBER 2005

12-BIT, OCTAL, ULTRALOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

• 2.7-V to 5.5-V Single Supply

The DAC7558 is a 12-bit, octal-channel, voltage

output DAC with exceptional linearity and

• 12-Bit Linearity and Monotonicity

monotonicity. Its proprietary architecture minimizes

• Rail-to-Rail Voltage Output

undesired transients such as code to code glitch and

• Settling Time: 5 µs (Max)

channel to channel crosstalk. The low-power

• Ultralow Glitch Energy: 0.1 nVs DAC7558 operates from a single 2.7-V to 5.5-V

supply. The DAC7558 output amplifiers can drive a

• Ultralow Crosstalk: –100 dB

2-k Ω , 200-pF load rail-to-rail with 5-µs settling time;

• Low Power: 1.8 mA (Max)

the output range is set using an external voltage

• Per-Channel Power Down: 2 µA (Max)

reference.

• Power-On Reset to Zero Scale and Mid Scale

The 3-wire serial interface operates at clock rates up

• SPI-Compatible Serial Interface: Up to 50 MHz to 50 MHz and is compatible with SPI, QSPI,

Microwire™, and DSP interface standards. The

• Simultaneous or Sequential Update

outputs of all DACs may be updated simultaneously

• Asynchronous Clear

or sequentially. The parts incorporate a

• Binary and Twos-Complement Capability

power-on-reset circuit to ensure that the DAC outputs

power up to zero volts and remain there until a valid

• Daisy-Chain Operation

write cycle to the device takes place. The parts

• 1.8-V to 5.5-V Logic Compatibility

contain a power-down feature that reduces the

• Specified Temperature Range: –40°C to 105°C

current consumption of the device to under 2 µA.

• Small, 5-mm x 5-mm, 32-Lead QFN Package

The small size and low-power operation makes the

DAC7558 ideally suited for battery-operated portable

applications. The power consumption is typically 7.5

mW at 5 V, 3.7 mW at 3 V, and reduces to 1 µW in

• Portable Battery-Powered Instruments

power-down mode.

• Digital Gain and Offset Adjustment

• Programmable Voltage and Current Sources

The DAC7558 is available in a 32-lead QFN package

and is specified over –40°C to 105°C.

• Programmable Attenuators

• Industrial Process Control

FUNCTIONAL BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Microwire is a trademark of National Semiconductor Corp..

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 12-BIT, OCTAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • • • • DESCRIPTION 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5 µs (Max) Ultralow Glitch Energy: 0.1 nVs Ultralow Crosstalk: –100 dB Low Power: 1.
PAGE 2
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design Bits ±0.35 ±1 LSB ±0.08 ±0.
PAGE 4
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 ELECTRICAL CHARACTERISTICS (Continued) VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS VDD, IOVDD (1) IDD(normal operation) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V 2.7 5.5 V 1.1 1.8 mA 1 1.7 0.2 2 0.
PAGE 5
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TIMING CHARACTERISTICS (1) (2) VDD = 2.7 V to 5.
PAGE 6
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 PIN DESCRIPTION VOUTE VFBE VOUTF VFBF VFBG VOUTH VOUTG VFBH RHB PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 25 16 VREF3 DCEN 26 15 SYNC VREF4 DGND RSTSEL 11 IOVDD RST 31 10 SDO VREF1 32 1 9 8 VREF2 2 3 4 5 6 7 VFBD 12 30 VOUTD AGND VFBB SDIN 29 VFBC VOUTC SCLK 13 VOUTB 14 28 VOUTA 27 VFBA PD VDD Terminal Functions TERMINAL NO.
PAGE 7
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 PIN DESCRIPTION (continued) Terminal Functions (continued) (1) 25 VREF4 Positive reference voltage input for DAC G and DAC H 26 DCEN Daisy-chain enable 27 PD Power down 28 VDD Analog voltage supply input 29 AGND (1) Analog ground 30 RSTSEL Reset select. If this pin is low, input coding is binary; if high, then 2s compliment. 31 RST Asynchronous reset. Active low.
PAGE 8
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vsDIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 VREF = 4.096 V VDD = 5 V Linearity Error − LSB Channel C 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Differential Linearity Error − LSB Differential Linearity Error − LSB Linearity Error − LSB 1 Channel D VREF = 4.
PAGE 9
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel G VREF = 4.096 V VDD = 5 V Linearity Error − LSB 1 Linearity Error − LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.5 0 −0.5 −0.25 Linearity Error − LSB 512 1024 1536 2048 2560 3072 3584 4096 VDD = 5 V 0 −0.5 0.5 0.25 0 −0.25 −0.
PAGE 10
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel C VREF = 2.5 V VDD = 2.7 V Linearity Error − LSB Linearity Error − LSB 1 0.5 0 −0.5 VREF = 2.5 V 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Differential Linearity Error − LSB 0.5 0 −0.5 0.5 0.25 0 −0.25 −0.
PAGE 11
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE VREF = 2.5 V 1 VDD = 2.7 V Linearity Error − LSB Channel G 0.5 0 −0.5 Channel H VREF = 2.5 V VDD = 2.7 V 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Figure 16. Figure 17.
PAGE 12
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.1 0.1 VDD = 5 V, VREF = 4.096 V VDD = 2.7 V, VREF = 2.5 V 0.05 Gain Error − % FSR Gain Error − % FSR 0.05 CHE 0 CHD −0.05 CHA 0 CHD −0.05 CHA, B, C, F, G, H −0.1 −40 −10 20 50 CH B, C, E, F, G, H −0.1 −40 80 TA − Free-Air Temperature − C Figure 20. Figure 21.
PAGE 13
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 0.15 Typical for all Channels VO − Output Voltage − V VO − Output Voltage − V Typical for all Channels VDD = 2.7 V, VREF = 2.5 V 0.1 0.05 5.40 DAC Loaded With FFFH VDD = VREF = 5.5 V 5.30 VDD = 5.5 V, VREF = 4.096 V DAC Loaded With 000H 0 0 5 10 5.
PAGE 14
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 1600 1600 All Channels Powered, No Load All DACs Powered, No Load, VREF = 2.5 V 1400 1400 I DD − Supply Current − µ A I DD − Supply Current − µ A VDD = 5.5 V, VREF = 4.096 V 1200 VDD = 2.7 V, VREF = 2.
PAGE 15
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 0.005 4000 3500 VDD = 2.7 V, VREF = 2.5 V E 0.0025 Output Error − V 3000 f − Frequency − Hz VDD = 5 V, VREF = 4.096, TA = 25 C 2500 2000 1500 D 0 A −0.0025 1000 B, C, F, G, H 500 0 600 700 800 900 1000 1100 1200 1300 1400 1500 −0.005 0 Figure 32. 1024 1536 2048 2560 3072 3584 4095 Figure 33. TOTAL ERROR - 2.
PAGE 16
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 3 5 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 1 2 1 VDD = 2.5 V, Output Loaded With 200 pF to GND, Code 41 to 4055 VDD = 5 V, Output Loaded With 200 pF to GND, Code 41 to 4055 0 0 t − Time − 5 s/div t − Time − 5 s/div Figure 36. Figure 37.
PAGE 17
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) DIGITAL FEEDTHROUGH ERROR CHANNEL-TO-CHANNEL CROSSTALK FOR A FULL-SCALE SWING VDD = 5 V, VREF = 4.096 V VO − Output Voltage VO − Output Voltage VDD = 5 V, VREF = 4.096 V Trigger Pulse Trigger Pulse t − Time − 400 nS/div t − Time − 400 nS/div Figure 40. Figure 41. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY −40 Total Harmonic Distortion − dB VDD = 5 V, VREF = 4.
PAGE 18
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 3-Wire Serial Interface The DAC7558 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1.
PAGE 19
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 THEORY OF OPERATION D/A SECTION OUTPUT BUFFER AMPLIFIERS The architecture of the DAC7558 consists of a string DAC followed by an output buffer amplifier. Figure 43 shows a generalized block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with up to 1000 pF to GND.
PAGE 20
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 Power Down The DAC7558 has a flexible power-down capability as described in Table 2 and Table 3. Individual channels can be powered down separately, or multiple channels can be powered down simultaneously. During a power-down condition, the user has flexibility to select the output impedance of each channel. If the PD pin is brought low, then all channels can simultaneously be powered down, with the output at high impedance state (High-Z).
PAGE 21
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 falling-edge setup time, t4. After SYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 24 clock pulses. Any data and clock pulses after the twenty-fourth falling edge of SCLK are ignored. No further serial data transfer occurs until SYNC is taken high and low again.
PAGE 22
DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 APPLICATION INFORMATION Waveform Generation Due to its exceptional linearity, low glitch, and low crosstalk, the DAC7558 is well suited for waveform generation (from DC to 10 kHz). The DAC7558 large-signal settling time is 5 µs, supporting an update rate of 200 KSPS. However, the update rates can exceed 1 MSPS if the waveform to be generated consists of small voltage steps between consecutive DAC updates.
PAGE 23
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7558IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 DAC7558IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7558IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 DAC7558IRHBT VQFN RHB 32 250 210.0 185.0 35.
PAGE 28
PAGE 29
PAGE 30
PAGE 31
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.