Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VSSOP 10

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FEATURES DESCRIPTION

APPLICATIONS

Input

DAC

String

DAC A

String

DAC B

String

DAC C

String

DAC D

Interface

Logic

Power-On

Reset

Power-Down

Logic

Buffer

REFIN

SCLK

SYNC

DIN

GND

OUT

DAC7554

SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004

12-BIT, QUAD, ULTRALOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

• 2.7-V to 5.5-V Single Supply

The DAC7554 is a quad-channel, voltage-output DAC

with exceptional linearity and monotonicity. Its pro-

• 12-Bit Linearity and Monotonicity

prietary architecture minimizes undesired transients

• Rail-to-Rail Voltage Output

such as code to code glitch and channel to channel

• Settling Time: 5 µs (Max)

crosstalk. The low-power DAC7554 operates from a

• Ultralow Glitch Energy: 0.1 nVs single 2.7-V to 5.5-V supply. The DAC7554 output

amplifiers can drive a 2-k Ω , 200-pF load rail-to-rail

• Ultralow Crosstalk: –100 dB

with 5-µs settling time; the output range is set using

• Low Power: 880 µA (Max)

an external voltage reference.

• Per-Channel Power Down: 2 µA (Max)

The 3-wire serial interface operates at clock rates up

• Power-On Reset to Zero Scale

to 50 MHz and is compatible with SPI, QSPI,

• SPI-Compatible Serial Interface: Up to 50 MHz Microwire, and DSP interface standards. The outputs

of all DACs may be updated simultaneously or

• Simultaneous or Sequential Update

sequentially. The parts incorporate a power-on-reset

• Specified Temperature Range: –40 ° C to 105 ° C

circuit to ensure that the DAC outputs power up to

• Small 10-Lead MSOP Package

zero volts and remain there until a valid write cycle to

the device takes place. The parts contain a

power-down feature that reduces the current con-

sumption of the device to under 1 µA.

• Portable Battery-Powered Instruments

• Digital Gain and Offset Adjustment The small size and low-power operation makes the

DAC7554 ideally suited for battery-operated portable

• Programmable Voltage and Current Sources

applications. The power consumption is typically 3.5

• Programmable Attenuators

mW at 5 V, 1.65 mW at 3 V, and reduces to 1 µW in

• Industrial Process Control

power-down mode.

The DAC7554 is available in a 10-lead MSOP pack-

age and is specified over –40 ° C to 105 ° C.

FUNCTIONAL BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 12-BIT, QUAD, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • DESCRIPTION 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5 µs (Max) Ultralow Glitch Energy: 0.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, REFIN = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design ±1 LSB ±0.08 ± 0.5 LSB ±12 mV Offset error Zero-scale error Bits ±0.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TIMING CHARACTERISTICS (1) (2) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS t1 (3) SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC falling edge to SCLK falling edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time (1) (2) (3) MIN VDD = 2.7 V to 3.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 PIN DESCRIPTION DGS Package (Top View) VOUTA VOUTB GND VOUTC VOUTD 1 10 2 9 3 8 4 7 5 6 REFIN SYNC VDD DIN SCLK Terminal Functions TERMINAL NO.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 1 Channel B VDD = 5 V Linearity Error − LSB VREF = 4.096 V 0.5 0 −0.5 −0.5 −1 −1 0.5 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 0.25 0 −0.25 −0.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 1 VREF = 2.5 V VDD = 2.7 V Linearity Error − LSB Linearity Error − LSB Channel A 0.5 0 −0.5 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 −0.5 0.5 0.25 0 −0.25 −0.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 10 10 VDD = 5 V, VREF = 4.096 V VDD = 2.7 V, VREF = 2.5 V Channel C 5 Channel D 0 Channel B Zero−Scale Error − mV Zero−Scale Error − mV Channel A Channel A 5 Channel C Channel D 0 Channel B −5 −40 −10 20 50 −5 −40 80 TA − Free-Air Temperature − °C 80 Figure 11.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 Typical for All Channels VDD = 2.7 V, Vref = 2.5 V 0.15 VO − Output Voltage − V VO − Output Voltage − V Typical for All Channels 0.1 VDD = 5.5 V, Vref = 4.096 V VDD = Vref = 5.5 V 5.40 5.30 0.05 DAC Loaded with 000h 0 0 5 10 ISINK − Sink Current − mA DAC Loaded with FFFh 5.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 800 700 VDD = 5.5 V, Vref = 4.096 V 600 VDD = 2.7 V, Vref = 2.5 V 500 All DACs Powered, No Load, Vref = 2.5 V 650 I DD − Supply Current − µ A I DD − Supply Current − µ A 700 400 300 200 600 550 500 450 100 All Channels Powered, No Load 0 −40 −10 20 50 80 TA − Free-Air Temperature − °C 400 2.7 110 3.8 4.1 4.5 4.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 2000 VDD = 5 V, Vref = 4.096 V, TA = 25 C Channel B Output VDD = 2.7 V, Vref = 2.5 V 6 Channel C Output 4 Total Error - mV f − Frequency − Hz 1500 1000 Channel A Output 2 0 −2 500 Channel D Output −4 0 −6 0 280 327 373 420 467 513 560 607 653 700 IDD − Current Consumption − A 6 TOTAL ERROR - 2.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 5 3 Vref = 2.5 V VDD = 2.7 V, Output Loaded With 200 pF to GND Code 41 to 4055 VDD = 5 V, Vref = 4.096 V Output Loaded With 200 pF to GND Code 41 to 4055 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 2 1 1 0 0 t − Time − 5 s/div Figure 27.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) CHANNEL-TO-CHANNEL CROSSTALK FOR A FULL-SCALE SWING VO - VO - (5 mV/Div) (5 mV/Div) DIGITAL FEEDTHROUGH ERROR Trigger Pulse Trigger Pulse Time - (400 nS/Div) Time - (400 nS/Div) Figure 30. Figure 31. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY THD − Total Harmonic Distortion − dB −40 VDD = 5 V, Vref = 4.
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DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 3-Wire Serial Interface The DAC7554 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1.
PAGE 15
DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 POWER-DOWN MODE In power-down mode, the DAC outputs are programmed to one of three output impedances, 1 kΩ, 100 kΩ, or floating. Table 2.
PAGE 16
DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 THEORY OF OPERATION D/A SECTION DAC External Reference Input The architecture of the DAC7554 consists of a string DAC followed by an output buffer amplifier. Figure 33 shows a generalized block diagram of the DAC architecture. There is a single reference input pin for the four DACs. The reference input is unbuffered. The user can have a reference voltage as low as 0.
PAGE 17
DAC7554 www.ti.com The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses.
PAGE 18
DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 Vtail DAC7554 R1 REF3140 R2 Vref _ REFIN DAC7554 Vdac + V out V ref R2 1 Din V tail R2 4096 R1 R1 VOUT OPA4130 Figure 35. Low-cost, Wide-swing Voltage Generator for Control Loop Applications The output voltage of the configuration is given by: (1) Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC7554IDGSR Package Package Pins Type Drawing VSSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7554IDGSR VSSOP DGS 10 2500 364.0 364.0 27.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.