Datasheet

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Power Down
Asynchronous Clear
IOVDD and Level Shifters
Daisy-Chain Operation
SERIAL INTERFACE
16-Bit Word and Input Shift Register
DAC7553
SLAS477 – SEPTEMBER 2005
register input data. Bit 13 (DB13) determines whether
the data is for DAC A, DAC B, or both DACs. Bit 12
The DAC7553 has a flexible power-down capability
(DB12) determines either normal mode or
as described in Table 2 . Individual channels could be
power-down mode (see Table 2 ). All channels are
powered down separately or all channels could be
updated when bits 15 and 14 (DB15 and DB14) are
powered down simultaneously. During a power-down
high.
condition, the user has flexibility to select the output
impedance of each channel. During power-down
The SYNC input is a level-triggered input that acts as
operation, each channel can have either 1-k Ω ,
a frame synchronization signal and chip enable. Data
100-k Ω , or Hi-Z output impedance to ground.
can only be transferred into the device while SYNC is
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC to SCLK
falling edge setup time, t
4
. After SYNC goes low,
The DAC7553 output is asynchronously set to
serial data is shifted into the device's input shift
midscale voltage immediately after the CLR pin is
register on the falling edges of SCLK for 16 clock
brought low. The CLR signal resets all internal
pulses.
registers and therefore behaves like the Power-On
Reset. The DAC7553 updates at the first rising edge
When DCEN is low, the SDO pin is brought to a Hi-Z
of the SYNC signal that occurs after the CLR pin is
state. The first 16 data bits that follow the falling edge
brought back to high.
of SYNC are stored in the shift register. The rising
edge of SYNC that follows the 16
th
data bit updates
the DAC(s). If SYNC is brought high before the 16
th
data bit, no action occurs.
The DAC7553 can be used with different logic
families that require a wide range of supply voltages When DCEN is high, data can continuously be shifted
(from 1.8 V to 5.5 V). To enable this useful feature, into the shift register, enabling the daisy-chain
the IOVDD pin must be connected to the logic supply operation. The SDO pin becomes active and outputs
voltage of the system. All DAC7553 digital input and SDIN data with 16 clock cycle delay. A rising edge of
output pins are equipped with level-shifter circuits. SYNC loads the shift register data into the DAC(s).
Level shifters at the input pins ensure that external The loaded data consists of the last 16 data bits
logic high voltages are translated to the internal logic received into the shift register before the rising edge
high voltage, with no additional power dissipation. of SYNC.
Similarly, the level shifter for the SDO pin translates
If daisy-chain operation is not needed, DCEN should
the internal logic high voltage (VDD) to the external
permanently be tied to a logic low voltage.
logic high level (IOVDD). For single-supply operation,
the IOVDD pin can be tied to the VDD pin.
When DCEN pin is brought high, daisy chaining is
enabled. The Serial Data Output (SDO) pin is
The DAC7553 is controlled over a versatile 3-wire
provided to daisy-chain multiple DAC7553 devices in
serial interface, which operates at clock rates up to
a system.
50 MHz and is compatible with SPI, QSPI, Microwire,
and DSP interface standards. As long as SYNC is high or DCEN is low, the SDO
pin is in a high-impedance state. When SYNC is
In daisy-chain mode (DCEN = 1) the DAC7553
brought low, the output of the internal shift register is
requires a falling SCLK edge after the rising SYNC, in
tied to the SDO pin. As long as SYNC is low and
order to initialize the serial interface for the next
DCEN is high, SDO duplicates the SDIN signal with a
update.
16-cycle delay. To support multiple devices in a daisy
chain, SCLK and SYNC signals are shared across all
devices, and SDO of one DAC7553 should be tied to
the SDIN of the next DAC7553. For n devices in such
The input shift register is 16 bits wide. DAC data is
a daisy chain, 16 n SCLK cycles are required to shift
loaded into the device as a 16-bit word under the
the entire input data stream. After 16 n SCLK falling
control of a serial clock input, SCLK, as shown in the
edges are received, following a falling SYNC, the
Figure 1 timing diagram. The 16-bit word, illustrated
data stream becomes complete and SYNC can be
in Table 1 , consists of four control bits followed by 12
brought high to update n devices simultaneously.
bits of DAC data. The 12-bit data is in 2s-complement
SDO operation is specified at a maximum SCLK
format, with 800H corresponding to 0-V output and
speed of 10 MHz.
7FFH corresponding to full-scale output (V
REF
– 1
LSB). Data is loaded MSB first (Bit 15) where the first
two bits (DB15 and DB14) determine if the input
register, DAC register, or both are updated with shift
16