Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) QFN 16

3 mm x 3 mm

Actual Size

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

Interface

Logic

Input

DAC

String

DAC A

Power-Down

Logic

Power-On

Reset

IOV

REFA

FBA

OUT

REFB

GND

CLR

DCEN

SDIN

SYNC

SCLK

Input

DAC

String

DAC B

FBB

OUT

SDO

FUNCTIONAL BLOCK DIAGRAM

DAC7553

SLAS477 – SEPTEMBER 2005

12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

• 2.7-V to 5.5-V Single Supply

The DAC7553 is a 12-bit, dual-channel,

voltage-output DAC with exceptional linearity and

• 12-Bit Linearity and Monotonicity

monotonicity. Its proprietary architecture minimizes

• Rail-to-Rail Voltage Output

undesired transients such as code-to-code glitch and

• Settling Time: 5 µs (Max)

channel-to-channel crosstalk. The low-power

• Ultralow Glitch Energy: 0.1 nVs DAC7553 operates from a single 2.7-V to 5.5-V

supply. The DAC7553 output amplifiers can drive a

• Ultralow Crosstalk: –100 dB

2-k Ω , 200-pF load rail-to-rail with 5-µs settling time;

• Low Power: 440 µA (Max)

the output range is set using an external voltage

• Per-Channel Power Down: 2 µA (Max)

reference.

• Power-On Reset to Midscale

The 3-wire serial interface operates at clock rates up

• 2s Complement Input Data Format to 50 MHz and is compatible with SPI, QSPI,

Microwire™, and DSP interface standards. The

• SPI-Compatible Serial Interface: Up to 50 MHz

outputs of all DACs may be updated simultaneously

• Daisy-Chain Capability

or sequentially. The parts incorporate a

• Asynchronous Hardware Clear

power-on-reset circuit to ensure that the DAC outputs

power up at midscale and remain there until a valid

• Simultaneous or Sequential Update

write cycle to the device takes place. The parts

• Specified Temperature Range: –40°C to 105°C

contain a power-down feature that reduces the

• Small 3-mm × 3-mm, 16-Lead QFN Package

current consumption of the device to under 2 µA.

The small size and low-power operation makes the

DAC7553 ideally suited for battery-operated portable

• Portable Battery-Powered Instruments

applications. The power consumption is typically

• Digital Gain and Offset Adjustment

1.5 mW at 5 V, 0.75 mW at 3 V, and reduces to 1 µW

in power-down mode.

• Programmable Voltage and Current Sources

• Programmable Attenuators

The DAC7553 is available in a 16-lead QFN package

and is specified over –40°C to 105°C.

• Industrial Process Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Microwire is a trademark of National Semiconductor Corp..

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
Actual Size 3 mm x 3 mm DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • • • DESCRIPTION 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5 µs (Max) Ultralow Glitch Energy: 0.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design ±1 LSB ±0.08 ±0.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS VDD,, IOVDD (3) IDD(normal operation) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V 2.7 5.5 V DAC active and excluding load current VIH = IOVDD and VIL = GND 300 440 250 400 0.2 2 0.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TIMING CHARACTERISTICS (1) (2) VDD = 2.7 V to 5.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 PIN DESCRIPTION VFBA VREFA CLR SDIN RGT PACKAGE (TOP VIEW) 1 16 15 14 13 12 2 11 3 10 4 9 6 7 8 SCLK SYNC IOVDD SDO DCEN 5 VFBB VREFB PD VOUTA VDD GND VOUTB Terminal Functions TERMINAL NO. 6 DESCRIPTION NAME 1 VOUTA Analog output voltage from DAC A 2 VDD Analog voltage supply input 3 GND Ground 4 VOUTB Analog output voltage from DAC B 5 VFBB DAC B amplifier sense input.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel A VREF = 4.096 V Linearity Error − LSB Linearity Error − LSB 1 VDD = 5 V 0.5 0 −0.5 VREF = 4.096 V 0.25 0 −0.25 −0.5 0 0 −0.5 512 1024 1536 2048 2560 3072 3584 4096 0.5 0.25 0 −0.25 −0.5 0 512 1024 Digital Input Code 2560 3072 3584 Figure 3.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 3 3 VDD = 2.7 V, VREF = 2.5 V 2 2 Zero-Scale Error − mV Zero-Scale Error − mV VDD = 5 V, VREF = 4.096 V Channel A 1 Channel B 1 Channel A 0 0 Channel B −1 −40 −10 20 50 −1 −40 80 TA − Free-Air Temperature − °C 50 Figure 6. Figure 7.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 Typical for All Channels VDD = 2.7 V, VREF = 2.5 V 0.15 VO − Output Voltage − V VO − Output Voltage − V Typical for All Channels 0.1 VDD = 5.5 V, VREF = 4.096 V VDD = VREF = 5.5 V 5.40 5.30 0.05 DAC Loaded with 000h 0 0 5 10 ISINK − Sink Current − mA DAC Loaded with FFFh 5.20 15 0 5 10 ISOURCE − Source Current − mA Figure 10. Figure 11.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 400 400 I DD − Supply Current − µ A I DD − Supply Current − µ A All DACs Powered, No Load, VREF = 2.5 V 350 VDD = 5.5 V, VREF = 4.096 V 300 VDD = 2.7 V, VREF = 2.5 V 250 350 300 250 All Channels Powered, No Load 200 −40 3.1 3.4 3.8 4.1 4.5 4.8 5.2 5.5 VDD − Supply Volatge − V Figure 14. Figure 15.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 4 1500 VDD = 5 V, VREF = 4.096 V, TA = 25 C VDD = 2.7 V, VREF = 2.5 V Total Error − mV f − Frequency − Hz 2 1000 Channel A Output 0 Channel B Output 500 −2 0 −4 0 239 249 259 269 279 289 299 309 319 IDD − Current Consumption − A Figure 18. 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code Figure 19. TOTAL ERROR - 2.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 5 3 VDD = 2.7 V, VREF = 2.5 V Output Loaded With 200 pF to GND Code 41 to 4055 VDD = 5 V, VREF = 4.096 V Output Loaded With 200 pF to GND Code 41 to 4055 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 2 1 1 0 0 t − Time − 5 s/div Figure 23. MIDSCALE GLITCH WORST-CASE GLITCH VO - VO - (5 mV/Div) (5 mV/Div) Figure 22.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) CHANNEL-TO-CHANNEL CROSSTALK FOR A FULL-SCALE SWING VO - VO - (5 mV/Div) (5 mV/Div) DIGITAL FEEDTHROUGH ERROR Trigger Pulse Trigger Pulse Time - (400 nS/Div) Time - (400 nS/Div) Figure 26. Figure 27. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY THD − Total Harmonic Distortion − dB −40 VDD = 5 V, VREF = 4.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) 3-Wire Serial Interface The DAC7553 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1. Serial Interface Programming CONTROL DATA BITS DAC(s) FUNCTION DB15 DB14 DB13 DB12 DB11-DB10 0 0 0 0 data A Single Channel Store. The TMP register of channel A is updated. 0 0 1 0 data B Single Channel Store. The TMP register of channel B is updated.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 THEORY OF OPERATION D/A SECTION OUTPUT BUFFER AMPLIFIERS The architecture of the DAC7553 consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a generalized block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with up to 1000 pF to GND.
PAGE 16
DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 Power Down The DAC7553 has a flexible power-down capability as described in Table 2. Individual channels could be powered down separately or all channels could be powered down simultaneously. During a power-down condition, the user has flexibility to select the output impedance of each channel. During power-down operation, each channel can have either 1-kΩ, 100-kΩ, or Hi-Z output impedance to ground.
PAGE 17
DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 INTEGRAL AND DIFFERENTIAL LINEARITY The DAC7553 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral linearity error is typically within (+/-) 0.35 LSBs, and differential linearity error is typically within (+/-) 0.08 LSBs. GLITCH ENERGY The DAC7553 uses a proprietary architecture that minimizes glitch energy.
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DAC7553 www.ti.com SLAS477 – SEPTEMBER 2005 V out V REF R2 1 Din V tail R2 4096 R1 R1 (1) Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once R2 and R1 set the gain to include some minimal over-range, a DAC7553 channel could be used to set the required offset voltage. Residual errors are not an issue for loop accuracy because offset and gain errors could be tolerated.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7553IRGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC7553IRGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7553IRGTR QFN RGT 16 3000 338.1 338.1 20.6 DAC7553IRGTT QFN RGT 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.