Datasheet

SCLK
SYNC
SDIN
D15 D14 D13
D12
D11 D1 D0 D15
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
D0
t
9
Input Word n Input Word n+1
Undefined
D15 D14
D0
Input Word n
t
10
SDO
CLR
DAC7552
SLAS442D –JANUARY 2005– REVISED JUNE 2011 www.ti.com
TIMING CHARACTERISTICS
(1) (2)
V
DD
= 2.7 V to 5.5 V, R
L
= 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
V
DD
= 2.7 V to 3.6 V 20
t
1
(3)
SCLK cycle time ns
V
DD
= 3.6 V to 5.5 V 20
V
DD
= 2.7 V to 3.6 V 10
t
2
SCLK HIGH time ns
V
DD
= 3.6 V to 5.5 V 10
V
DD
= 2.7 V to 3.6 V 10
t
3
SCLK LOW time ns
V
DD
= 3.6 V to 5.5 V 10
V
DD
= 2.7 V to 3.6 V 4
SYNC falling edge to SCLK falling edge setup
t
4
ns
time
V
DD
= 3.6 V to 5.5 V 4
V
DD
= 2.7 V to 3.6 V 5
t
5
Data setup time ns
V
DD
= 3.6 V to 5.5 V 5
V
DD
= 2.7 V to 3.6 V 4.5
t
6
Data hold time ns
V
DD
= 3.6 V to 5.5 V 4.5
V
DD
= 2.7 V to 3.6 V 0
t
7
SCLK falling edge to SYNC rising edge ns
V
DD
= 3.6 V to 5.5 V 0
V
DD
= 2.7 V to 3.6 V 20
t
8
Minimum SYNC HIGH time ns
V
DD
= 3.6 V to 5.5 V 20
V
DD
= 2.7 V to 3.6 V 10
t
9
SCLK falling edge to SDO valid ns
V
DD
= 3.6 V to 5.5 V 10
V
DD
= 2.7 V to 3.6 V 10
t
10
CLR pulse width low ns
V
DD
= 3.6 V to 5.5 V 10
(1) All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See Serial Write Operation timing diagram Figure 1.
(3) Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
Figure 1. Serial Write Operation
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