Datasheet

DAC7552
www.ti.com SLAS442D –JANUARY 2005– REVISED JUNE 2011
Asynchronous Clear
The SYNC input is a level-triggered input that acts as
a frame synchronization signal and chip enable. Data
The DAC7552 output is asynchronously set to
can only be transferred into the device while SYNC is
zero-scale voltage immediately after the CLR pin is
low. To start the serial data transfer, SYNC should be
brought low. The CLR signal resets all internal
taken low, observing the minimum SYNC to SCLK
registers and therefore behaves like the Power-On
falling edge setup time, t
4
. After SYNC goes low,
Reset. The DAC7552 updates at the first rising edge
serial data is shifted into the device's input shift
of the SYNC signal that occurs after the CLR pin is
register on the falling edges of SCLK for 16 clock
brought back to high.
pulses.
IOVDD and Level Shifters The state of the daisy chain enable pin, DCEN,
determines when the input data word is latched into
The DAC7552 can be used with different logic
the converter and when the output can be updated.
families that require a wide range of supply voltages
When DCEN is low, daisy chain mode is disabled and
(from 1.8 V to 5.5 V). To enable this useful feature,
the SDO pin is brought to a Hi-Z state. The first 16
the IOVDD pin must be connected to the logic supply
data bits that follow the first falling edge of SYNC are
voltage of the system. All DAC7552 digital input and
stored in the shift register. Immediately following the
output pins are equipped with level-shifter circuits.
16th falling edge of SCLK, the converter latches the
Level shifters at the input pins ensure that external
data word into the DAC and it updates immediately. If
logic high voltages are translated to the internal logic
SYNC is brought high before the 16th data bit, the
high voltage, with no additional power dissipation.
data word is ignored and no action occurs.
Similarly, the level shifter for the SDO pin translates
the internal logic high voltage (AVDD) to the external When DCEN is high, daisy chain mode is enabled
logic high level (IOVDD). For single-supply operation, causing data that is input to the shift register to be
the IOVDD pin can be tied to the AVDD pin. passed through and shifted out. The SDO pin
becomes active and outputs the SDIN data with a 16
clock cycle delay. In this case, a rising edge of SYNC
SERIAL INTERFACE
is required in order to load the shift register data into
The DAC7552 is controlled over a versatile 3-wire
the DAC. The loaded data consists of the last 16 data
serial interface, which operates at clock rates up to
bits received into the shift register before the rising
50 MHz and is compatible with SPI, QSPI, Microwire,
edge of SYNC.
and DSP interface standards.
If daisy-chain operation is not needed, DCEN should
In daisy-chain mode (DCEN = 1), the DAC7552
permanently be tied to a logic low voltage.
requires a falling SCLK edge after the rising SYNC, in
order to initialize the serial interface for the next
Daisy-Chain Operation
update.
When DCEN pin is brought high, daisy chaining is
enabled. Serial Data Output (SDO) pin is provided to
16-Bit Word and Input Shift Register
daisy-chain multiple DAC7552 devices in a system.
The input shift register is 16 bits wide. DAC data is
As long as SYNC is high or DCEN is low, the SDO
loaded into the device as a 16-bit word under the
pin is in a high-impedance state. When SYNC is
control of a serial clock input, SCLK, as shown in the
brought low the output of the internal shift register is
Figure 1 timing diagram. The 16-bit word, illustrated
tied to the SDO pin. As long as SYNC is low and
in Table 1, consists of four control bits followed by 12
DCEN is high, SDO duplicates SDIN signal with a
bits of DAC data. The data format is straight binary
16-cycle delay. To support multiple devices in a daisy
with all zeroes corresponding to 0-V output and all
chain, SCLK and SYNC signals are shared across all
ones corresponding to full-scale output (V
REF
– 1
devices, and SDO of one DAC7552 should be tied to
LSB). Data is loaded MSB first (bit 15) where the first
the SDIN of the next DAC7552. For n devices in such
two bits (DB15 and DB14) determine if the input
a daisy chain, 16n SCLK cycles are required to shift
register, DAC register, or both are updated with shift
the entire input data stream. After 16n SCLK falling
register input data. Bit 13 (DB13) determines whether
edges are received, following a falling SYNC, the
the data is for DAC A, DAC B, or both DACs. Bit 12
data stream becomes complete and SYNC can be
(DB12) determines either normal mode or
brought high to update n devices simultaneously.
power-down mode (see Table 2). All channels are
SDO operation is specified at a maximum SCLK
updated when bits 15 and 14 (DB15 and DB14) are
speed of 10 MHz.
high.
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