Datasheet

SCLK
SYNC
SDIN
D15 D14 D13
D12
D11 D1 D0 D15
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
D0
t
9
Input Word n Input Word n+1
Undefined
D15 D14
D0
Input Word n
t
10
SDO
CLR
DAC7551-Q1
SLAS767 –JUNE 2011 www.ti.com
SERIAL WRITE OPERATION
Figure 1. Serial Write Operation Timing Diagram
TIMING CHARACTERISTICS
(1) (2)
All specifications at –40°C to +105°C, V
DD
= 2.7V to 5.5V, and R
L
= 2kΩ to GND (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
V
DD
= 2.7V to 3.6V 20
t
1
(3)
SCLK cycle time ns
V
DD
= 3.6V to 5.5V 20
V
DD
= 2.7V to 3.6V 6.5
t
2
SCLK HIGH time ns
V
DD
= 3.6V to 5.5V 6.5
V
DD
= 2.7V to 3.6V 6.5
t
3
SCLK LOW time ns
V
DD
= 3.6V to 5.5V 6.5
V
DD
= 2.7V to 3.6V 4
t
4
SYNC falling edge to SCLK falling edge setup time ns
V
DD
= 3.6V to 5.5V 4
V
DD
= 2.7V to 3.6V 3
t
5
Data setup time ns
V
DD
= 3.6V to 5.5V 3
V
DD
= 2.7V to 3.6V 3
t
6
Data hold time ns
V
DD
= 3.6V to 5.5V 3
t
1
–
V
DD
= 2.7V to 3.6V 0
10ns
(4)
t
7
SCLK falling edge to SYNC rising edge ns
V
DD
= 3.6V to 5.5V 0 t
1
–
10ns
(4)
V
DD
= 2.7V to 3.6V 20
t
8
Minimum SYNC HIGH time ns
V
DD
= 3.6V to 5.5V 20
V
DD
= 2.7V to 3.6V 10
t
9
SCLK falling edge to SDO valid ns
V
DD
= 3.6V to 5.5V 10
V
DD
= 2.7V to 3.6V 10
t
10
CLR pulse width low ns
V
DD
= 3.6V to 5.5V 10
(1) All input signals are specified with t
R
= t
F
= 1ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See Figure 1, Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at V
DD
= 2.7V to 5.5V.
(4) SCLK falling edge to SYNC rising edge time shold not exceed (t
1
– 10ns) in order to latch the correct data.
6 Copyright © 2011, Texas Instruments Incorporated