Datasheet

V
DD
V H
REF
V L
REF
V
FB
V
OUT
GND
IOV
DD
SDO
SDIN
SCLK
SYNC
CLR
1
2
3
4
5
6
12
11
10
9
8
7
DAC7751
Thermal
Pad
(1)
DAC7551-Q1
www.ti.com SLAS767 –JUNE 2011
PIN CONFIGURATION
Pin Descriptions
PIN
NO. NAME DESCRIPTION
1 V
DD
Analog voltage supply input
2 V
REF
H Positive reference voltage input
3 V
REF
L Negative reference voltage input
4 V
FB
DAC amplifier sense input.
5 V
OUT
Analog output voltage from DAC
6 GND
(1)
Ground.
Asynchronous input to clear the DAC registers. When CLR is low, the DAC register is set to 000h and the output
7 CLR
voltage to 0V.
Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out
8 SYNC
to the DAC7551-Q1.
9 SCLK Serial clock input
10 SDIN Serial data input
11 SDO Serial data output
12 IOV
DD
I/O voltage supply input
(1) Thermal pad should be connected to GND.
Copyright © 2011, Texas Instruments Incorporated 5