Datasheet

DAC7551-Q1
SLAS767 –JUNE 2011 www.ti.com
SERIAL INTERFACE As long as SYNC is high, the SDO pin is in a
high-impedance state. When SYNC is brought low
The DAC7551-Q1 is controlled over a versatile 3-wire
the output of the internal shift register is tied to the
serial interface, which operates at clock rates up to
SDO pin. As long as SYNC is low, SDO duplicates
50MHz and is compatible with SPI, QSPI, Microwire,
the SDIN signal with a 16-cycle delay. To support
and DSP interface standards.
multiple devices in a daisy chain, SCLK and SYNC
signals are shared across all devices, and SDO of
16-Bit Word and Input Shift Register
one DAC7551-Q1 should be tied to the SDIN of the
next DAC7551-Q1. For n devices in such a daisy
The input shift register is 16 bits wide. DAC data are
chain, 16n SCLK cycles are required to shift the
loaded into the device as a 16-bit word under the
entire input data stream. After 16n SCLK falling
control of a serial clock input, SCLK, as shown in
edges are received, following a falling SYNC, the
Figure 1, the Serial Write Operation timing diagram.
data stream becomes complete and SYNC can be
The 16-bit word, illustrated in Table 1, consists of four
brought high to update n devices simultaneously.
control bits followed by 12 bits of DAC data. The data
SDO operation is specified at a maximum SCLK
format is straight binary with all zeroes corresponding
speed of 10MHz.
to 0V output and all ones corresponding to full-scale
output (V
REF
– 1LSB). Data are loaded MSB first (bit
In daisy-chain mode, the use of a weak pull-down
15) where the first two bits (DB15 and DB14) are
resistor on the SDO output pin, which provides the
don't care bits. Bit 13 and bit 12 (DB13 and DB12)
SDIN data for the next device in the chain, is
determine either normal mode operation or
recommended. For standalone operation, the
power-down mode (see Table 1).
maximum clock speed is 50MHz. For daisy-chain
operation, the maximum clock speed is 10MHz.
The SYNC input is a level-triggered input that acts as
a frame synchronization signal and chip enable. Data
can only be transferred into the device while SYNC is INTEGRAL AND DIFFERENTIAL LINEARITY
low. To start the serial data transfer, SYNC should be
The DAC7551-Q1 uses precision thin-film resistors
taken low, observing the minimum SYNC to SCLK
providing exceptional linearity and monotonicity.
falling edge setup time, t
4
. After SYNC goes low,
Integral linearity error is typically within ±0.35LSBs,
serial data is shifted into the device input shift register
and differential linearity error is typically within
on the falling edges of SCLK for 16 clock pulses.
±0.08LSBs.
The SPI interface is enabled after SYNC becomes
low and the data are continuously shifted into the shift
GLITCH ENERGY
register at each falling edge of SCLK. When SYNC is
The DAC7551-Q1 uses a proprietary architecture that
brought high, the last 16 bits stored in the shift
minimizes glitch energy. The code-to-code glitches
register are latched into the DAC register, and the
are so low that they are usually buried within the
DAC updates.
wide-band noise and cannot be easily detected. The
DAC7551-Q1 glitch is typically well under 0.1nV-s.
Daisy-Chain Operation
Such low glitch energy provides more than a ten-time
Daisy-chain operation is used for updating
improvement over industry alternatives.
serially-connected devices on the rising edge of
SYNC.
Table 1. Serial Interface Programming
CONTROL DATA BITS
DB13 DB12
DB15 DB14 (PD1) (PD0) DB11–DB0 FUNCTION
X X 0 0 data Normal mode
X X 0 1 X Powerdown 1kΩ
X X 1 0 X Powerdown 100kΩ
X X 1 1 X Powerdown Hi-Z
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