Datasheet

DAC7551-Q1
www.ti.com SLAS767 –JUNE 2011
Power-On Reset
OUTPUT BUFFER AMPLIFIERS
On power up, all registers are cleared and the DAC
The output buffer amplifier is capable of generating
channel is updated with zero-scale voltage. The DAC
rail-to-rail voltages on its output, giving an output
output remains in this state until valid data are
range of 0V to V
DD
. It is capable of driving a load of
written. This setup is particularly useful in applications
2kΩ in parallel with up to 1000pF to GND. The source
where it is important to know the state of the DAC
and sink capabilities of the output amplifier can be
output while the device is powering up. In order to not
seen in the typical curves. The slew rate is 1.8V/μs
turn on ESD protection devices, V
DD
and IOV
DD
with a half-scale settling time of 3μs with the output
should be applied before any other pin (such as
unloaded.
V
REF
H) is brought high. The power-up sequence of
V
DD
and IOV
DD
is irrelevant. Therefore, IOV
DD
can be
DAC External Reference Input
brought up before V
DD
, or vice-versa.
The DAC7551-Q1 contains V
REF
H and V
REF
L
reference inputs, which are unbuffered. The V
REF
H
Power Down
reference voltage can be as low as 0.25V, and as
The DAC7551-Q1 has a flexible power-down
high as V
DD
because there is no restriction of
capability. During a power-down condition, the user
headroom and footroom from any reference amplifier.
has flexibility to select the output impedance of the
It is recommended to use a buffered reference in the
DAC. During power-down operation, the DAC can
external circuit (for example, the REF3140). The input
have either 1kΩ, 100kΩ, or Hi-Z output impedance to
impedance is typically 100kΩ.
ground.
Amplifier Sense Input
Asynchronous Clear
The DAC7551-Q1 contains an amplifier feedback
The DAC7551-Q1 output is asynchronously set to
input pin, V
FB
. For voltage output operation, V
FB
must
zero-scale voltage immediately after the CLR pin is
be externally connected to V
OUT
. For better DC
brought low. The CLR signal resets all internal
accuracy, this connection should be made at load
registers and therefore behaves like the Power-On
points. The V
FB
pin is also useful for a variety of
Reset. The DAC7551-Q1 updates at the first rising
applications, including digitally-controlled current
edge of the SYNC signal that occurs after the CLR
sources. The feedback input pin is internally
pin is brought back to high.
connected to the DAC amplifier negative input
terminal through a 100kΩ resistor. The amplifier
IOVDD and Level Shifters
negative input terminal internally connects to ground
The DAC7551-Q1 can be used with different logic
through another 100kΩ resistor (Figure 26). These
families that require a wide range of supply voltages.
connections form a gain-of-two, noninverting,
To enable this useful feature, the IOV
DD
pin must be
amplifier configuration. Overall gain remains one
connected to the logic supply voltage of the system.
because the resistor string has a divide-by-two
All DAC7551-Q1 digital input and output pins are
configuration. The resistance seen at the V
FB
pin is
equipped with level-shifter circuits. Level shifters at
approximately 200kΩ to ground.
the input pins ensure that external logic-high voltages
are translated to the internal logic-high voltage, with
no additional power dissipation. Similarly, the level
shifter for the SDO pin translates the internal
logic-high voltage (V
DD
) to the external logic-high
level (IOV
DD
). For single-supply operation, the IOV
DD
pin can be tied to the V
DD
pin.
Copyright © 2011, Texas Instruments Incorporated 13