Datasheet

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SERIAL INTERFACE
16-Bit Word and Input Shift Register
INTEGRAL AND DIFFERENTIAL LINEARITY
GLITCH ENERGY
Daisy-Chain Operation
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
As long as SYNC is high, the SDO pin is in a
high-impedance state. When SYNC is brought low
The DAC7551 is controlled over a versatile 3-wire
the output of the internal shift register is tied to the
serial interface, which operates at clock rates up to
SDO pin. As long as SYNC is low, SDO duplicates
50MHz and is compatible with SPI, QSPI, Microwire,
the SDIN signal with a 16-cycle delay. To support
and DSP interface standards.
multiple devices in a daisy chain, SCLK and SYNC
signals are shared across all devices, and SDO of
one DAC7551 should be tied to the SDIN of the next
DAC7551. For n devices in such a daisy chain, 16 n
The input shift register is 16 bits wide. DAC data are
SCLK cycles are required to shift the entire input
loaded into the device as a 16-bit word under the
data stream. After 16 n SCLK falling edges are
control of a serial clock input, SCLK, as shown in
received, following a falling SYNC, the data stream
Figure 1 , the Serial Write Operation timing diagram.
becomes complete and SYNC can be brought high
The 16-bit word, illustrated in Table 1 , consists of
to update n devices simultaneously. SDO operation
four control bits followed by 12 bits of DAC data. The
is specified at a maximum SCLK speed of 10MHz.
data format is straight binary with all zeroes
corresponding to 0V output and all ones
In daisy-chain mode, the use of a weak pull-down
corresponding to full-scale output (V
REF
– 1LSB).
resistor on the SDO output pin, which provides the
Data are loaded MSB first (bit 15) where the first two
SDIN data for the next device in the chain, is
bits (DB15 and DB14) are don't care bits. Bit 13 and
recommended. For standalone operation, the
bit 12 (DB13 and DB12) determine either normal
maximum clock speed is 50MHz. For daisy-chain
mode operation or power-down mode (see Table 1 ).
operation, the maximum clock speed is 10MHz.
The SYNC input is a level-triggered input that acts as
a frame synchronization signal and chip enable. Data
can only be transferred into the device while SYNC
The DAC7551 uses precision thin-film resistors
is low. To start the serial data transfer, SYNC should
providing exceptional linearity and monotonicity.
be taken low, observing the minimum SYNC to SCLK
Integral linearity error is typically within ± 0.35LSBs,
falling edge setup time, t
4
. After SYNC goes low,
and differential linearity error is typically within
serial data is shifted into the device input shift
± 0.08LSBs.
register on the falling edges of SCLK for 16 clock
pulses.
The SPI interface is enabled after SYNC becomes
The DAC7551 uses a proprietary architecture that
low and the data are continuously shifted into the
minimizes glitch energy. The code-to-code glitches
shift register at each falling edge of SCLK. When
are so low that they are usually buried within the
SYNC is brought high, the last 16 bits stored in the
wide-band noise and cannot be easily detected. The
shift register are latched into the DAC register, and
DAC7551 glitch is typically well under 0.1nV-s. Such
the DAC updates.
low glitch energy provides more than a ten-time
improvement over industry alternatives.
Daisy-chain operation is used for updating
serially-connected devices on the rising edge of
SYNC.
Table 1. Serial Interface Programming
CONTROL DATA BITS
DB13 DB12
DB15 DB14 (PD1) (PD0) DB11–DB0 FUNCTION
X X 0 0 data Normal mode
X X 0 1 X Powerdown 1k Ω
X X 1 0 X Powerdown 100k Ω
X X 1 1 X Powerdown Hi-Z
13
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