Datasheet

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OUTPUT BUFFER AMPLIFIERS
Power Down
DAC External Reference Input
Asynchronous Clear
Amplifier Sense Input
IOVDD and Level Shifters
Power-On Reset
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
order to not turn on ESD protection devices, V
DD
and
IOV
DD
should be applied before any other pin (such
The output buffer amplifier is capable of generating
as V
REF
H) is brought high. The power-up sequence
rail-to-rail voltages on its output, giving an output
of V
DD
and IOV
DD
is irrelevant. Therefore, IOV
DD
can
range of 0V to V
DD
. It is capable of driving a load of
be brought up before V
DD
, or vice-versa.
2k Ω in parallel with up to 1000pF to GND. The
source and sink capabilities of the output amplifier
can be seen in the typical curves. The slew rate is
1.8V/ µ s with a half-scale settling time of 3 µ s with the The DAC7551 has a flexible power-down capability.
output unloaded. During a power-down condition, the user has
flexibility to select the output impedance of the DAC.
During power-down operation, the DAC can have
either 1k Ω , 100k Ω , or Hi-Z output impedance to
The DAC7551 contains V
REF
H and V
REF
L reference
ground.
inputs, which are unbuffered. The V
REF
H reference
voltage can be as low as 0.25V, and as high as V
DD
because there is no restriction of headroom and
footroom from any reference amplifier. The DAC7551 output is asynchronously set to
zero-scale voltage immediately after the CLR pin is
It is recommended to use a buffered reference in the
brought low. The CLR signal resets all internal
external circuit (for example, the REF3140 ). The
registers and therefore behaves like the Power-On
input impedance is typically 100k Ω .
Reset. The DAC7551 updates at the first rising edge
of the SYNC signal that occurs after the CLR pin is
brought back to high.
The DAC7551 contains an amplifier feedback input
pin, V
FB
. For voltage output operation, V
FB
must be
externally connected to V
OUT
. For better DC
The DAC7551 can be used with different logic
accuracy, this connection should be made at load
families that require a wide range of supply voltages.
points. The V
FB
pin is also useful for a variety of
To enable this useful feature, the IOV
DD
pin must be
applications, including digitally-controlled current
connected to the logic supply voltage of the system.
sources. The feedback input pin is internally
All DAC7551 digital input and output pins are
connected to the DAC amplifier negative input
equipped with level-shifter circuits. Level shifters at
terminal through a 100k Ω resistor. The amplifier
the input pins ensure that external logic-high
negative input terminal internally connects to ground
voltages are translated to the internal logic-high
through another 100k Ω resistor (Figure 26 ). These
voltage, with no additional power dissipation.
connections form a gain-of-two, noninverting,
Similarly, the level shifter for the SDO pin translates
amplifier configuration. Overall gain remains one
the internal logic-high voltage (V
DD
) to the external
because the resistor string has a divide-by-two
logic-high level (IOV
DD
). For single-supply operation,
configuration. The resistance seen at the V
FB
pin is
the IOV
DD
pin can be tied to the V
DD
pin.
approximately 200k Ω to ground.
On power up, all registers are cleared and the DAC
channel is updated with zero-scale voltage. The DAC
output remains in this state until valid data are
written. This setup is particularly useful in
applications where it is important to know the state of
the DAC output while the device is powering up. In
12
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