Datasheet

DAC7513
14
SBAS157A
www.ti.com
the advantage that the output impedance of the part is known
while the part is in power-down mode. There are three
different options: the output is connected internally to GND
through a 1kΩ resistor; a 100kΩ resistor; or it is left open-
circuited (High-Z). The output stage is illustrated in Figure 5.
All linear circuitry is shut down when the power-down mode
is activated, however, the contents of the DAC register are
unaffected when in power-down. The time to exit
power-down is typically 2.5µs for V
DD
= 5V, and 5µs for
V
DD
= 3V, (see the Typical Chacteristics for more information).
FIGURE 5. Output Stage During Power-Down.
Resistor
String DAC
Amplifier
Power-down
Circuitry
Resistor
Network
V
OUT
V
FB
MICROPROCESSOR
INTERFACING
DAC7513 TO 8051 INTERFACE
Figure 6 shows a serial interface between the DAC7513 and
a typical 8051-type microcontroller. The setup for the inter-
face is as follows: TXD of the 8051 drives SCLK of the
DAC7513, while RXD drives the serial data line of the part;
the
SYNC signal is derived from a bit programmable pin on
the port. In this case, port line P3.3 is used. When data is to
be transmitted to the DAC7513, P3.3 is taken LOW. The
8051 transmits data only in 8-bit bytes; thus only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left LOW after the first eight bits are transmitted,
a second write cycle is initiated to transmit the second byte
FIGURE 6. DAC7513 to 80C51/80L51 Interface.
FIGURE 7. DAC7513 to Microwire Interface.
80C51/80L51
(1)
P3.3
TXD
RXD
DAC7513
(1)
SYNC
SCLK
D
IN
NOTE: (1) Additional pins omitted for clarity.
SYNC
SCLK
D
IN
Microwire
TM
CS
SK
SO
DAC7513
(1)
NOTE: (1) Additional pins omitted for clarity.
of data, and P3.3 is taken HIGH following the completion of
this cycle. The 8051 outputs the serial data in a format which
has the LSB first. The DAC7513 requires its data with the
MSB as the first bit received, thus, the 8051 transmit routine
must therefore take this into account and mirror the data as
needed.
DAC7513 TO Microwire INTERFACE
Figure 7 shows an interface between the DAC7513 and any
Microwire compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
DAC7513 on the rising edge of the SK signal.
DAC7513 TO 68HC11 INTERFACE
Figure 8 shows a serial interface between the DAC7513 and
the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC7513, while the MOSI output drives the
serial data line of the DAC. The
SYNC signal is derived from
a port line (PC7), similar to what was done for the 8051.
The 68HC11 must be configured so that its CPOL bit is a 0
and its CPHA bit is a 1, this configuration causes data
appearing on the MOSI output as valid on the falling edge of
SCK. When data is being transmitted to the DAC, the
SYNC
line is taken LOW (PC7). Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data to the DAC7513, PC7 is left LOW after
the first eight bits are transferred, and a second serial write
operation is performed to the DAC and PC7 is taken HIGH
at the end of this procedure.
FIGURE 8. DAC7513 to 68HC11 Interface.
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
DAC7513
(1)
NOTE: (1) Additional pins omitted for clarity.