Datasheet

DAC7513
13
SBAS157A
www.ti.com
DB13 DB12 OPERATING MODE
0 0 Normal Operation
Power-Down Modes
0 1 Output 1kΩ to GND
1 0 Output 100kΩ to GND
1 1 High-Z
The inverting input of the output amplifier is brought out to the
V
FB
pin. This allows for better accuracy in critical applications
by tying the V
FB
point and the amplifier output together directly
at the load. Other signal conditioning circuitry can also be
connected between these points for specific applications.
SERIAL INTERFACE
The DAC7513 has a 3-wire serial interface SYNC , SCLK, and
D
IN
, which is compatible with SPI, QSPI, and Microwire
interface standards as well as most Digital Signal Processors
(DSPs). See the Serial Write Operation timing diagram for an
example of a typical write sequence.
The write sequence begins by bringing the
SYNC line LOW,
data from the D
IN
line is clocked into the 16-bit shift register
on the falling edge of SCLK. The serial clock frequency can
be as high as 30MHz, making the DAC7513 compatible with
high-speed DSPs. On the 16th falling edge of the serial
clock, the last data bit is clocked in and the programmed
function is executed (i.e., a change in the DAC register
contents and/or a change in the mode of operation).
At this point, the
SYNC line may be kept LOW or brought
HIGH. In either case, it must be brought HIGH for a minimum
of 33ns before the next write sequence so that a falling edge
of
SYNC can initiate the next write sequence. As the SYNC
buffer draws more current when the SYNC signal is HIGH
than it does when it is LOW,
SYNC must be idled LOW
between write sequences for lowest power operation of the
part. As mentioned above, however, it must be brought HIGH
again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide, as shown in
Figure 3. The first two bits are
don’t cares . The next two bits
(PD1 and PD0) are control bits that control which mode of
operation the part is in (normal mode or any one of three
power-down modes). There is a more complete description
of the various modes in the Power-Down Modes section. The
next 12 bits are the data bits. These are transferred to the
DAC register on the 16th falling edge of SCLK.
X X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TABLE I. Modes of Operation for the DAC7513.
FIGURE 3. Data Input Register.
FIGURE 4.
SYNC Interrupt Facility.
DB15 DB0
CLK
SYNC
D
IN
Invalid Write Sequence:
SYNC HIGH before 16th Falling Edge
Valid Write Sequence: Output Updates
on the 16th Falling Edge
DB15 DB0 DB15 DB0
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept LOW for
at least 16 falling edges of SCLK and the DAC is updated on
the 16th falling edge. However, if
SYNC is brought HIGH
before the 16th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset and the write
sequence is seen as invalid. Neither an update of the DAC
register contents or a change in the operating mode occurs,
as shown in Figure 4.
POWER-ON RESET
The DAC7513 contains a power-on reset circuit that controls
the output voltage during power-up. Upon power up, the DAC
register is filled with zeros and the output voltage is 0V; it
remains there until a valid write sequence is made to the
DAC. This is useful in applications where it is important to
know the state of the output of the DAC while it is in the
process of powering up.
POWER-DOWN MODES
The DAC7513 contains four separate modes of operation,
which are programmable by setting two bits (PD1 and PD0)
in the control register. Table I shows how the state of the bits
corresponds to the mode of operation of the device.
When both bits are set to 0, the part works normally with its
normal power consumption of 115µA at 5V. However, for the
three power-down modes, the supply current falls to 200nA
at 5V (50nA at 3V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has