Datasheet

InvalidWriteSequence:
HIGHbefore16thFallingEdgeSYNC
ValidWriteSequence:
OutputUpdateson16thFallingEdge
CLK
SYNC
D
IN
DB15 DB0 DB15 DB0
DAC5311
DAC6311
DAC7311
SBAS442B –AUGUST 2008–REVISED MAY 2013 www.ti.com
SERIAL INTERFACE the DACx311 compatible with high-speed DSPs. On
the 16th falling edge of the serial clock, the last data
The DACx311 has a 3-wire serial interface (SYNC,
bit is clocked in and the programmed function is
SCLK, and DIN) compatible with SPI, QSPI, and
executed.
Microwire interface standards, as well as most DSPs.
See the Serial Write Operation timing diagram for an At this point, the SYNC line may be kept low or
example of a typical write sequence. brought high. In either case, it must be brought high
for a minimum of 20ns before the next write
DACx311 Input Shift Register sequence so that a falling edge of SYNC can initiate
the next write sequence. As previously mentioned, it
The input shift register is 16 bits wide, as shown in
must be brought high again before the next write
Table 2. The first two bits (PD0 and PD1) are
sequence.
reserved control bits that set the desired mode of
operation (normal mode or any one of three power-
DACx311 SYNC Interrupt
down modes) as indicated in Table 5.
In a normal write sequence, the SYNC line is kept
The remaining data bits are either 12 (DAC7311), 10
low for at least 16 falling edges of SCLK and the DAC
(DAC6311), or 8 (DAC5311) data bits, followed by
is updated on the 16th falling edge. However,
don't care bits, as shown in Table 2, Table 3, and
bringing SYNC high before the 16th falling edge acts
Table 4, respectively.
as an interrupt to the write sequence. The shift
register is reset and the write sequence is seen as
The write sequence begins by bringing the SYNC line
invalid. Neither an update of the DAC register
low. Data from the DIN line are clocked into the 16-bit
contents nor a change in the operating mode occurs,
shift register on each falling edge of SCLK. The serial
as shown in Figure 79.
clock frequency can be as high as 50MHz, making
Table 2. DAC5311 8-Bit Data Input Register
DB15 DB14 DB6 DB5 DB0
PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
Table 3. DAC6311 10-Bit Data Input Register
DB15 DB14 DB4 DB3 DB0
PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
Table 4. DAC7311 12-Bit Data Input Register
DB15 DB14 DB2 DB1 DB0
PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
Figure 79. DACx311 SYNC Interrupt Facility
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