Datasheet

13
®
DAC716
FIGURE 10a. Parallel Bus Connection.
FIGURE 10b. Timing Diagram For Figure 10a.
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Clock
Data
Data Latch 1
Data Latch 2
Data Latch 3
Update

DAC 1 DAC 2 DAC 3
SDI
A0
A1
CLK
CLR
DAC716
DAC 1
DAC716
DAC 2
DAC716
DAC 3
SDO
Data
Data Latch 1
Data Latch 2
Data Latch 3
Up Date
CLK
4
2
3
1
16
SDI
A0
A1
CLK
CLR SDO
4
2
3
1
16
SDI
A0
A1
CLK
CLR SDO
4
2
3
1
16
5
5
5
CLR