Datasheet

11
®
DAC716
FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update.
FIGURE 8b. Timing Diagram For Figure 8a.
FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210
Clock
Data
Data Latch
Update
DAC 3 DAC 2 DAC 1
SDI
A0
A1
CLK
CLR
DAC716
DAC 1
SDO
Data
Data Latch
Up Date
CLK
4
2
3
1
16
+5V
SDI
A0
A1
CLK
CLR
DAC716
DAC 2
SDO
4
2
3
1
16
+5V
SDI
A0
A1
CLK
CLR
DAC716
DAC 3
SDO
4
2
3
1
16
+5V
5
5
5
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