Datasheet

DAC714
2
SBAS032A
www.ti.com
PIN CONFIGURATION
Top View
CLK
A
0
A
1
SDI
SDO
DCOM
+V
CC
ACOM
DAC714
CLR
–V
CC
Gain Adjust
Offset Adjust
V
REF OUT
R
BPO
R
FB2
V
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PIN DESCRIPTIONS
PIN LABEL DESCRIPTION
1 CLK Serial Data Clock
2A
0
Enable for Input Register (Active Low)
3A
1
Enable for D/A Latch (Active Low)
4 SDI Serial Data Input
5 SDO Serial Data Output
6 DCOM Digital Ground
7+V
CC
Positive Power Supply
8 ACOM Analog Ground
9V
OUT
D/A Output
10 R
FB2
±10V Range Feedback Output
11 R
BPO
Bipolar Offset
12 V
REF OUT
Voltage Reference Output
13 Offset Adjust Offset Adjust
14 Gain Adjust Gain Adjust
15 –V
CC
Negative Power Supply
16 CLR Clear
SO/DIP
+V
CC
to Common .................................................................... 0V to +17V
–V
CC
to Common .................................................................... 0V to –17V
+V
CC
to –V
CC
....................................................................................... 34V
ACOM to DCOM ............................................................................... ±0.5V
Digital Inputs to Common............................................. –1V to (V
CC
–0.7V)
External Voltage Applied to BPO and Range Resistors .................... ±V
CC
V
REF OUT
..........................................................Indefinite Short to Common
V
OUT
............................................................... Indefinite Short to Common
SDO ............................................................... Indefinite Short to Common
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under
Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
PACKAGE/ORDERING INFORMATION