Datasheet

10kW
3
4
6
±10VV
OUT
DAC712
9.75kW
IDAC
0mA-2mA
15kW
R
20kW
3
0Vto+10V
R
10kW
4
170W 250W
Internal
+10VReference
V
REFOUT
GainAdjust
(1)
BipolarOffsetAdjust
(1)
R
340W
1
R
500W
2
R
FB
V
REFA
5
R
FB
V
REFB
0Vto10V
5kW
10kW
+10V
10kW
-10V
(2)
(3)
(4)
DIGITAL INTERFACE
BUS INTERFACE SINGLE-BUFFERED OPERATION
enabled by connecting
A
0
to DCOM. If
A
1
is not used
A
0
is the enable control for the DATA INPUT LATCH.
A
1
is the enable for the D/A LATCH. WR is used to
strobe data into latches enabled by
A
0
and
A
1
. Refer
TRANSPARENT INTERFACE
transparent by asserting
A
0
,
A
1
, and WR LOW, and
DAC712
www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
(1) For no external adjustments, pins 4 and 6 are not connected. External Resistors R
1
to R
4
tolerance is ± 1% values. Range of adjustment
is at least ± 0.3% FSR.
(2) Suggested op amps: OPA177GP, GS or OPA604AP, AU .
(3) Suggested op amps: single OPA177GP, GS or dual OPA2604AP, AU .
(4) Suggested D/A converters: dual DAC7800 (serial input, 12-bit resolution); dual DAC7801 (8-bit port input, 12-bit resolution); dual
DAC7802 (12-bit port input, 12-bit resolution); dual DAC7545 (12-bit port input, 12-bit resolution); or single DAC8043 (serial input, 12-bit
resolution). BIPOLAR (complete): DAC813 (use 11-bit resolution for 0V to +10V output; no op-amps required).
Figure 14. Gain and Offset Adjustment Using D/A Converters
The DAC712 has 16-bit, double-buffered data bus To operate the DAC712 interface as a single-buffered
interface with control lines for easy interface to latch, the DATA INPUT LATCH is permanently
interface to a 16-bit bus. The double-buffered feature
permits update of several D/A converters
to enable the D/A converter, it should be connected
simultaneously.
to DCOM as well. For this mode of operation, the
width of WR must be at least 80ns minimum to pass
data through the DATA INPUT LATCH and into the
D/A LATCH.
to the block diagram of Figure 8 and to Figure 1 .
CLR sets the INPUT DATA LATCH to all zeros and
The digital interface of the DAC712 can be made
the D/A LATCH to a code that gives bipolar 0V at the
D/A converter output.
asserting CLR HIGH.
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