Information

Texas Instruments Signal Chain Guide 2013 | 99
Interface
Crosspoint and Redundancy MUX
Get more information:
www.ti.com/product/SN65LVCP114
14.2 Gbps Quad Mux, Linear-Redriver with Signal Conditioning
SN65LVCP114
The SN65LVCP114 is an asynchronous, protocol-agnostic, low-latency quad mux,
linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device
linearly compensates for channel loss in backplane and active-cable applications.
The architecture of SN65LVCP114 is designed to work effectively with ASIC or FPGA
pr
oducts implementing digital equalization using decision feedback equalizer (DFE)
technology. This device preserves the integrity (composition) of the received signal,
ensuring optimum DFE and system performance and provides a low-power mux-demux,
linear-redriver solution while extending the effectiveness of DFE.
SN65LVCP114 functional block diagram
Key Features
• Quad2:1mux/1:2demux
• Multi-rateoperationupto14.2
Gbps serial data rate
•
Linearreceiverequalizationwhich
increases margin at system level of
decision feedback equalizer
•
Bandwidth:18GHz,typical
• Per-LaneP/Npairinversion
• Portorsinglelaneswitching
• Lowpower:150mW/channel,typical
• Loopbackmodeonallthreeports
• I
2
C control in addition to GPIO
• DIAGmodethatoutputsdataofline
side port to both fabric side ports
•
2.5-V/3.3-Vsinglepowersupply
Applications
• High-speedredundancyswitchin
telecom and data communication
• Backplaneinterconnectfor10G-KR,
16 GFC
Linear Driver
Linear Receive
Equalization
2X 1
1X 2
Linear Driver
Linear Receive
Equalization
Digital Control
SEL [x]
LP [x]
DIAG
PWD #
I
2
C _SEL
I
2
C Logic
EQA 0
ADD 2/EQC 1
SN65LVCP114
AINP [3:0]
AINN [3:0]
BINP [3:0]
BINN [3:0]
CINP [3:0]
CINN [3:0]
COUTP [3:0]
COUTN [3:0]
AOUTP [3:0]
AOUTN [3:0]
BOUTP [3:0]
BOUTN [3:0]
CS
4
3
EQB 0
EQC 0
SDA
SCL
DIS _AGC [x]
3
4
LN _[x]_EN
FST _SW
ADD 0/EQA 1
ADD 1/EQB 1
GAIN _[x]
VOD _[x]
3
3