Information

92 | Signal Chain Guide 2013 Texas Instruments
Fanout Buffers (continued)
Zero-Delay Buffers
*Suggested resale price in U.S. dollars in quantities of 1,000. See www.ti.com/hirel for HiRel options.
Device Description Input Level
Output
Level
Frequency
(MHz)
V
CC
(V)
Jitter (Peak-to-Peak [P-P]
or Cycle-to-Cycle [C-C]) Phase Error
Char. Temp.
(ºC)
HiRel
Avail. P
ackage Price*
Differential-Ended
CDCV850 1:10 Differential Clock Driver SSTL_2/
Universal
SSTL_2 60 to 140 2.5 C-C: ±30 ps
(100 to 133 MHz )
–80/150 ps
(133 MHz )
–40 to 85 N TSSOP-48 2.20
CDCV855 1:4 Differential Clock Driver SSTL_2/L
VTTL SSTL_2 60 to 180 2.5 C-C: ±50 ps
(100 to 180 MHz )
±100 ps
(100 to
180 MHz )
–40 to 85 N TSSOP-28 1.15
CDCV857 1:10 PLL Differential Clock Driver
for DDR 200/266/333, SSC
SSTL_2/LVTTL SSTL_2 60 to 200 2.5 C-C: ±75 ps
(100 to 200 MHz )
–150/50 ps
(200 MHz )
0 to 85 N TSSOP-48 4.20
CDCV857A 1:10 PLL Differential Clock Driver
for DDR 200/266/333, SSC
SSTL_2/LVTTL SSTL_2 60 to 180 2.5 C-C: ±50 ps
(100 to 180 MHz )
±100 ps
(100 to
180 MHz )
0 to 85 N TSSOP-48,
µBGA-56
2.90
CDCV857B 1:10 PLL Differential Clock Driver
for DDR 200/266/333, SSC
SSTL_2/LVTTL SSTL_2 60 to 200 2.5 C-C: ±50 ps
(100 to 200 MHz )
±50 ps (min/max)
(100 to
200 MHz )
0 to 70 N TSSOP-48,
µBGA-56
3.65
CDCV857BI 1:10 PLL Differential Clock Driver
for DDR 200/266/333, SSC
SSTL_2/LVTTL SSTL_2 60 to 200 2.5 C-C: ±50 ps
(100 to 200 MHz )
±50 ps (min/max)
(100 to
200 MHz )
–40 to 85 N TSSOP-48,
µBGA-56
3.35
CDCVF857 1:10 PLL Differential Clock Driver
for DDR 200/266/333/400, SSC
SSTL_2/LVTTL SSTL_2 60 to 220 2.5 C-C: ±35 ps
(133 to 200 MHz )
±50 ps (min/max)
(100 to
200 MHz )
–40 to 85 N TSSOP-48,
QFN-48,
µBGA-56
3.60
CDCU877 1:10 PLL Differential Clock Driver
for DDR2 Applications, SSC
SSTL_18 SSTL_18 10 to 400 1.8 C-C: ±30 ps
(190 to 340 MHz )
±50 ps –40 to 85 N µBGA-52,
QFN-40
3.05
CDCU877A 1:10 PLL Differential Clock Driver
for DDR2 Applications, SSC
SSTL_18 SSTL_18 10 to 400 1.8 C-C: ±30 ps
(190 to 340 MHz )
±50 ps –40 to 85 N µBGA-52,
QFN-40
3.05
CDCU877B 1:10 PLL Differential Clock Driver
for DDR2 400/533, SSC
SSTL_18 SSTL_18 10 to 340 1.8 C-C: ±30 ps
(190 to 340 MHz )
±50 ps –40 to 85 N µBGA-52 3.05
CDCUA877 1:10 PLL Differential Clock
Driver for DDR2 400~800, SSC,
8-mA Output
SSTL_18 SSTL_18 125 to 410 1.8 C-C: ±40 ps
(200 to 333 MHz )
±50 ps –40 to 85 N µBGA-52 3.35
CDCU2A877 1:10 PLL Differential Clock
Driver for DDR2 400~800, SSC,
16-mA Output
SSTL_18 SSTL_18 125 to 410 1.8 C-C: ±40 ps
(160 to 410 MHz )
±50 ps 0 to 70 N µBGA-52 3.05
Single-Ended
CDCVF2505 1:5 PLL Clock Driver for SDR/
PC133+, SSC
LVTTL LVTTL 24 to 200 3.3 C-C: |70| ps (typ)
(66 to 200 MHz )
±150 ps
(66 to 166 MHz )
–40 to 85 Y TSSOP-8,
SOIC-8
0.95
CDCVF2509A 1:9 PLL Clock Driver for SDR/
PC133+, SSC
LVTTL LVTTL 50 to 175 3.3 C-C: |65| ps (typ)
(100 to 166 MHz )
±125 ps
(66 to 166 MHz )
0 to 85 N TSSOP-24 3.90
CDCVF2510A 1:10 PLL Clock Driver for SDR/
PC133+,
SSC
LVTTL LVTTL 50 to 175 3.3 C-C: |65| ps (typ)
(100 to 166 MHz )
±125 ps
(66 to 166 MHz )
0 to 85 N TSSOP-24 2.60
Device Description Input Level Output Level
Frequency
(MHz)
V
CC
(V)
Propagation
Delay
Output Skew
(max) (ps)
Char.
Temp.
(ºC)
Hi-Rel
Avail. Package Price*
Dividers
CDCM1804 1:3 LVPECL + 1:1 LVCMOS
Buffer with Dividers
LVPECL LVPECL/LVCMOS 800 3.3 600 ps
(LVPECL), 2.6
ns (LVCMOS)
30 ps (LVPECL),
1.6 ns (LVCMOS)
–40 to 85 N QFN-24 5.90
CDCM1802 1:1 LVCMOS + 1:1 LVPECL
Buffer with Dividers
LVPECL LVPECL/LVCMOS 800 3.3 600 ps
(LVPECL), 2.6
ns (LVCMOS)
1.6 ns (typ) –40 to 85 N QFN-16 4.70
CDCP1803 1:3 LVPECL Clock Buffer with
Programmable Divider
LVPECL/LVDS LVPECL 0 to 800 3.3 320 to 600 ps) 30 ps –40 to 85 Y QFN-24 3.15
CDCE18005 3:5 LVPECL/LVDS/LVCMOS
Buffer with Dividers
LVPECL/LVDS/
LVCMOS
LVPECL/LVDS/
LVCMOS
DC to
1.5 GHz
3.3 4 ns 75 ps –40 to 85 N QFN-48 6.00
CDCUN1208LP Ultra-Low-Power, 2:8 Fan-out
Buffer with Universal Inputs
and Outputs
HCSL, LVDS, LVCMOS HCSL, LVDS,
LVCMOS
0 to 400 3.3/2.5/1.8 3.8 ns 50ps –40 to 85 N QFN-32 5.00
LMK01801 14-Output Universal Fanout
Buffer with Divider and Delay
LVPECL/LVDS/LVCMOS LVPECL/LVDS/
LVCMOS
1 kHz to 3.1
GHz
3.3 — 32 ps (typ, DIFF-to-
DIFF), 830 ps (typ,
DIFF-to-CMOS)
–40 to 85 N LLP-48 6.75
Clocks and Timing
Clocks Distribution (Fanout Buffers, Zero-Delay Buffers)
*Suggested resale price in U.S. dollars in quantities of 1,000.