Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History
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5
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8
16
15
14
13
12
11
10
9
SCL
SDA
GND
V B
OUT
V D
OUT
V F
OUT
V H
OUT
CLR
LDAC
ADDR0
AV
DD
V A
OUT
V C
OUT
V E
OUT
V G
OUT
V
REFIN
DACx578
NC
AV
DD
V A
OUT
V C
OUT
V E
OUT
V G
OUT
NC
GND
V B
OUT
V D
OUT
V F
OUT
V H
OUT
1
2
3
4
5
6
18
17
16
15
14
13
DACx578
7 8 9 10 11 12
24 23 22 21
20
19
NC
V
REFIN
RSTSEL
ADDR1
ADDR0
CLR
NC
NC
LDAC
TWOC
SCL
SDA
(Thermal pad)
1
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
PIN CONFIGURATIONS
PW PACKAGE
RGE PACKAGE
TSSOP-16
QFN-24
(TOP VIEW)
(TOP VIEW)
(1) It is recommended to connect the thermal
pad to GND for better thermal dissipation.
PIN DESCRIPTIONS
PACKAGE
NAME DESCRIPTION
16-Pin 24-PIN
1 22 LDAC Load DACs
2 11 ADDR0 3-state address input
3 2 AV
DD
Power-supply input, 2.7V to 5.5V
4 3 V
OUT
A Analog output voltage from DAC A
5 4 V
OUT
C Analog output voltage from DAC C
6 5 V
OUT
E Analog output voltage from DAC E
7 6 V
OUT
G Analog output voltage from DAC G
8 8 V
REFIN
Positive reference input
9 12 CLR Asynchronous clear input
10 13 V
OUT
H Analog output voltage from DAC H
11 14 V
OUT
F Analog output voltage from DAC F
12 15 V
OUT
D Analog output voltage from DAC D
13 16 V
OUT
B Analog output voltage from DAC B
14 17 GND Ground reference point for all circuitry on the device
Serial data input. Data are clocked into or out of the input register. This pin is a bidirectional,
15 19 SDA
open-drain data line that should be connected to the supply voltage with an external pull-up resistor.
16 20 SCL Serial clock input. Data can be transferred at rates up to 3.4MHz. Schmitt-trigger logic input.
— 1 NC Not internally connected
— 7 NC Not internally connected
— 9 RSTSEL Reset select pin. RSTSEL high resets device to mid-scale; RSTSEL low resets device to zero-scale.
— 10 ADDR1 3-state address input
— 18 NC Not internally connected
Twos complement select. If the TWOC pin is pulled high, the DAC registers use twos complement
— 21 TWOC
format; if TWOC is pulled low, the DAC registers use straight binary format.
— 23 NC Not internally connected
— 24 NC Not internally connected
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