Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History

IN 1 2
O UT REF REF
n
1
D R + R R2
V = V Gain V
R R1
2
æ ö
æ ö
æ ö æ ö
´ ´ ´ - ´
ç ÷
ç ÷
ç ÷ç ÷
ç ÷
è øè ø
è ø
è ø
IN
OUT
n
10 D
V = 5V
2
´
æ ö
-
ç ÷
è ø
Pull-Up Resistors
1k to 10k (typ)W W
Microcontroller or
Microprocessor
with I C Port
2
VDD
5
6
7
8
12
11
10
9
V D
OUT
V F
OUT
V H
OUT
CLR
V C
OUT
V E
OUT
V G
OUT
V
REFIN
DACx578
Top
View
1
2
3
4
16
15
14
13
SCL
SDA
GND
V B
OUT
LDAC
ADDR0
AV
DD
V A
OUT
SCL
SDA
V
OUT
V
REFIN
/
V
REFOUT
V
REF
EXT
+6V
±5V
-6V
OPA703
DACx578
10 Fm 0.1 Fm
R
1
10kW
R
2
10kW
Serial Interface
GND
AV
DD
AV
DD
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
APPLICATION INFORMATION
DAC NOISE PERFORMANCE
MICROPROCESSOR INTERFACING
Output noise spectral density at the V
OUTX
pin versus
A basic connection diagram to the SCL and SDA pins
frequency is depicted in Figure 55 for full-scale,
of the DACx578 is shown in Figure 119. The
midscale, and zero-scale input codes. The typical
DACx578 interfaces directly to standard mode, fast
noise density reduces to 104nV/√Hz at 1kHz for mid
mode and high speed mode of 2-Wire compatible
scale code with external reference as shown in
serial interfaces. The DACx578 does not perform
Figure 55. Integrated output noise between 0.1Hz
clock stretching (pulling SCL low), as a result it is not
and 10Hz is close to 3µV
PP
(midscale), as shown in
necessary to provide for this function unless other
Figure 56.
devices on the same bus require this function. Pull-up
resistors are required on both the SDA and SCL lines
BIPOLAR OPERATION USING THE DACx578
as the bus-drivers are open-drain. The size of these
The DACx578 family of products is designed for
pull-up resistors depends on the operating speed and
single-supply operation, but a bipolar output range is
capacitance of the bus lines. Higher value resistors
also possible using the circuit in either Figure 118.
consume less power but increase transition time on
Rail-to-rail operation at the amplifier output is
the bus limiting the bus speed. Long bus lines have
achievable using an OPA703 as the output amplifier.
higher capacitance and require smaller pull-up
resistors to compensate. The resistors should not be
The output voltage for any input code can be
too small; if they are, bus drivers may not be able to
calculated with Equation 2.
pull the bus lines low.
(2)
Where:
D
IN
= decimal equivalent of the binary code that
is loaded to the DAC register. It can range from 0
to 4095 (12 bit), 0 to 1023 (10 bit), and 0 to 255
(8 bit)
n = resolution in bits
Gain = 1
(3)
This result has an output voltage range of ±5V with
000h corresponding to a -5V output and FFFh
corresponding to a +5V output for the 12 bit
DAC7578.
Figure 119. Typical Connections of the DACx578
Figure 118. Bipolar Output Range Using External
Reference at 5V
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Link(s): DAC5578 DAC6578 DAC7578