Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History
Amplifier
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
V X
OUT
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
For example: C3, C2, C1, and C0 = '0100' and DB14 CLR pin low clears the contents of all DAC registers
and DB13 = '11' represent a power-down condition and all DAC buffers and replaces the code with the
with High-Z output impedance for a selected channel. code determined by the clear code register. The clear
DB14 and DB13 = '01' represents a power-down code register can be written to by applying the
condition with 1kΩ output impedance, while DB14 commands showed in Table 14. The default setting of
and DB13 = '10' represents a power-down condition the clear code register sets the output of all DAC
with 100kΩ output impedance. channels to 0V when the CLR pin is brought low. The
CLR pin is falling-edge triggered; therefore, the
Table 16. DAC Operating Modes device exits clear code mode on the falling edge of
the acknowledge signal that follows LSDB of the next
PD1 PD0
write sequence. If the CLR pin is executed (brought
(DB14) (DB13) DAC OPERATING MODES
low) during a write sequence, this write sequence is
0 0 Power on selected DACs
aborted and the DAC registers and DAC buffers are
0 1 Power down selected DACs, 1kΩ to GND
cleared as described above.
1 0 Power down selected DACs, 100kΩ to GND
When performing a software reset of the device, the
1 1 Power down selected DACs, High-Z to GND
clear code register is reset to the default mode (DB5
= '0', DB4 = '0'). Setting the clear code register to
Spacer
DB4 = '1' and DB5 = '1' ignores any activity on the
external CLR pin.
SOFTWARE RESET FUNCTION
The DACx578 contains a software reset feature.
When the software reset feature is executed, the
device (all DAC channels) are reset to the power-on
reset code. All registers inside the device are reset to
the respective default settings. The DACx578 has an
additional feature of switching straight to high speed
mode after reset. Table 17 shows all the different
modes of the software reset function.
Table 17. Software Reset Modes
Figure 117. Output Stage During Power-Down
DB15 DB14 OPERATING MODES
Default Software reset. Equivalent to
0 0
Power-on-Reset
CLEAR CODE REGISTER AND CLR PIN
Software reset and set part in High Speed
x 1
The DACx578 contains a clear code register. The
Mode
clear code register can be accessed via the serial
Software reset and maintain High Speed
1 0
interface (I
2
C) and is user configurable. Bringing the
Mode state
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