Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
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Table 14. Control Matrix for Write Commands (see Table 10, Table 11, and Table 12 for 8-bit, 10-bit, and 12-bit mapping) (continued)
COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION
C3 C2 C1 C0 A3 A2 A1 A0 DATA[7:0] X X X X X X X X General data format for 8-bit DAC5578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[9:2] D1 D0 X X X X X X General data format for 10-bit DAC6578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[11:4] D3 D2 D1 D0 X X X X General data format for 12-bit DAC7578
When all DAC bits are set to '1', selected DACs ignore
the LDAC pin.
0 1 1 0 X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X X X X
When all DAC bits are set to '0', selected DAC registers
update according to the LDAC pin.
Software Reset
0 1 1 1 X X X X 0 0 X X X X X X X X X X X X X X Software reset (default). Same as power-on reset (POR).
0 1 1 1 X X X X 0 1 X X X X X X X X X X X X X X Software reset that sets device into High-Speed mode
0 1 1 1 X X X X 1 0 X X X X X X X X X X X X X X Software reset that maintains High-Speed mode state
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