Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
Table 14. Control Matrix for Write Commands (see Table 10, Table 11, and Table 12 for 8-bit, 10-bit, and 12-bit mapping) (continued)
COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION
C3 C2 C1 C0 A3 A2 A1 A0 DATA[7:0] X X X X X X X X General data format for 8-bit DAC5578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[9:2] D1 D0 X X X X X X General data format for 10-bit DAC6578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[11:4] D3 D2 D1 D0 X X X X General data format for 12-bit DAC7578
0 0 1 1 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed
Broadcast mode, write to all input registers and update
0 0 1 1 1 1 1 1 Data[11:4] Data[3:0] X X X X
all DAC registers
Write to Selected DAC Input Register and Update All DAC Registers (Global Software LDAC)
Write to DAC input register for channel A and update all
0 0 1 0 0 0 0 0 Data[11:4] Data[3:0] X X X X
DAC registers
Write to DAC input register for channel B and update all
0 0 1 0 0 0 0 1 Data[11:4] Data[3:0] X X X X
DAC registers
Write to DAC input register for channel C and update all
0 0 1 0 0 0 1 0 Data[11:4] Data[3:0] X X X X
DAC registers
Write to DAC input register for channel D and update all
0 0 1 0 0 0 1 1 Data[11:4] Data[3:0] X X X X
DAC registers
Write to DAC input register for channel E and update all
0 0 1 0 0 1 0 0 Data[11:4] Data[3:0] X X X X
DAC registers
Write to DAC input register for channel F and update all
0 0 1 0 0 1 0 1 Data[11:4] Data[3:0] X X X X
DAC registers
Write to DAC input register for channel G and update all
0 0 1 0 0 1 1 0 Data[11:4] Data[3:0] X X X X
DAC registers
Write to DAC input register for channel H and update all
0 0 1 0 0 1 1 1 Data[11:4] Data[3:0] X X X X
DAC registers
0 0 1 0 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed
Broadcast mode, write to all input registers and update
0 0 1 0 1 1 1 1 Data[11:4] Data[3:0] X X X X
all DAC registers
Power-Down Register
0 1 0 0 X X X X X PD1 PD0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X
0 1 0 0 X X X X X 0 0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X Each DAC bit set to '1' powers on selected DACs
Each DAC bit set to '1' powers down selected DACs.
0 1 0 0 X X X X X 0 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X
V
OUT
connected to GND through 1kΩ pull-down resistor
Each DAC bit set to '1' powers down selected DACs.
0 1 0 0 X X X X X 1 0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X V
OUT
connected to GND through 100kΩ pull-down
resistor
Each DAC bit set to '1' powers down selected DACs.
0 1 0 0 X X X X X 1 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X
V
OUT
is High Z
Clear Code Register
0 1 0 1 X X X X X X X X X X X X X X CL1 CL0 X X X X
0 1 0 1 X X X X X X X X X X X X X X 0 0 X X X X Write to clear code register, CLR pin clears to zero scale
0 1 0 1 X X X X X X X X X X X X X X 0 1 X X X X Write to clear code register, CLR pin clears to midscale
0 1 0 1 X X X X X X X X X X X X X X 1 0 X X X X Write to clear code register, CLR pin clears to full scale
0 1 0 1 X X X X X X X X X X X X X X 1 1 X X X X Write to clear code register disables CLR pin
LDAC Register
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