Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
Table 7. Most Significant Data Byte (MSDB)
MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
Table 8. Least Significant Data Byte (LSDB)
MSB LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Table 9. Broadcast Address Command
MSB LSB
1 0 0 0 1 1 1 0
Table 10. DAC5578 Data Input Register Format
DB23 DB15 DB8 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
|--------- Command and Address Bits ---------| |---------------------- Data Bits ----------------------| |--------------------- Don't Care ---------------------|
Table 11. DAC6578 Data Input Register Format
DB23 DB15 DB6 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
|--------- Command and Address Bits ---------| |------------------------------ Data Bits ------------------------------| |------------- Don't Care -------------|
Table 12. DAC7578 Data Input Register Format
DB23 DB15 DB4 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
|--------- Command and Address Bits ---------| |-------------------------------------- Data Bits --------------------------------------| |----- Don't Care -----|
Table 13. Read Sequence
S MSB … R/W(0) ACK MSB … LSB ACK Sr MSB … R/W(1) ACK MSB … LSB ACK MSB … LSB ACK
Address Byte Command/Access Byte Sr Address Byte MSDB LSDB
From master Slave From master Slave From master slave From Slave Master From Slave Master
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