Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History

DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
Table 4. Address Format For TSSOP-16 (PW) Package
SLAVE ADDRESS ADDR0
1001 000 0
1001 010 1
1001 100 Float
register is being accessed when writing to or reading
Command and Access (CA) Byte
from the DACx578. See Table 6 for a list of write and
The command and access byte, as shown in Table 5,
read commands.
controls which command is executed and which
Table 5. Command and Access Byte
MSB LSB
C3 C2 C1 C0 A3 A2 A1 A0
Command bits
(1)
Access bits
(1)
(1) See Table 6 for bit selection.
Table 6. Command and Access Byte Format
(1)
C3 C2 C1 C0 A3 A2 A1 A0 DESCRIPTION
Write Sequences
0 0 0 0 A3 A2 A1 A0 Write to DAC input register channel n
0 0 0 1 A3 A2 A1 A0 Select to update DAC register channel n
Write to DAC input register channel n, and update all DAC registers
0 0 1 0 A3 A2 A1 A0
(global software LDAC)
0 0 1 1 A3 A2 A1 A0 Write to DAC input register channel n, and update DAC register channel n
0 1 0 0 X X X X Power down/on DAC
0 1 0 1 X X X X Write to clear code register
0 1 1 0 X X X X Write to LDAC register
0 1 1 1 X X X X Software reset
Read Sequences
0 0 0 0 A3 A2 A1 A0 Read from DAC input register channel n
0 0 0 1 A3 A2 A1 A0 Read from DAC register channel n
0 1 0 0 X X X X Read from DAC power down register
0 1 0 1 X X X X Read from clear code register
0 1 1 0 X X X X Read from LDAC register
Access Sequences
C3 C2 C1 C0 0 0 0 0 DAC channel A
C3 C2 C1 C0 0 0 0 1 DAC channel B
C3 C2 C1 C0 0 0 1 0 DAC channel C
C3 C2 C1 C0 0 0 1 1 DAC channel D
C3 C2 C1 C0 0 1 0 0 DAC channel E
C3 C2 C1 C0 0 1 0 1 DAC channel F
C3 C2 C1 C0 0 1 1 0 DAC channel G
C3 C2 C1 C0 0 1 1 1 DAC channel H
C3 C2 C1 C0 1 1 1 1 All DAC channels, broadcast update
(1) Any sequences other than the ones listed are invalid; improper use can cause incorrect device operation.
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