Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATIONS
- TIMING DIAGRAM
- TIMING REQUIREMENTS
- TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
- TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
- THEORY OF OPERATION
- DIGITAL-TO-ANALOG CONVERTER (DAC)
- RESISTOR STRING
- OUTPUT AMPLIFIER
- TWO-WIRE, I2C-COMPATIBLE INTERFACE
- DACx578 I2C UPDATE SEQUENCE
- POWER-ON RESET TO ZERO-SCALE OR MIDSCALE
- LDAC FUNCTIONALITY
- POWER-DOWN COMMANDS
- CLEAR CODE REGISTER AND CLR PIN
- SOFTWARE RESET FUNCTION
- OPERATING EXAMPLES: DAC7578
- Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
- Example 2: Power-Down Channel B, C, and H with Hi-Z Output
- Example 3: Read-back the value of the input register of DAC Channel G
- Example 4: Write multiple bytes of data to Channel F. Write Full Scale and then Quarter Scale to Channel F
- Example 5: Write Mid Scale and then Full Scale to all DAC channels.
- APPLICATION INFORMATION
- PARAMETER DEFINITIONS
- Revision History
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
At AV
DD
= 2.7V to 5.5V and over –40°C to +125°C, unless otherwise noted.
DAC5578, DAC6578, DAC7578
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
STATIC PERFORMANCE
(1)
Resolution 8 Bits
DAC5578 Relative accuracy Measured by the line passing through codes 4 and 250 ±0.01 ±0.25 LSB
Differential nonlinearity ±0.01 ±0.25 LSB
Resolution 10 Bits
Measured by the line passing through codes 12 and
DAC6578 Relative accuracy ±0.06 ±0.5 LSB
1012
Differential nonlinearity ±0.03 ±0.5 LSB
Resolution 12 Bits
Measured by the line passing through codes 30 and
DAC7578 Relative accuracy ±0.3 ±1 LSB
4050
Differential nonlinearity ±0.1 ±0.25 LSB
Extrapolated from two-point line passing through two
Offset error 0.5 ±4 mV
codes
(2)
, unloaded
Offset error drift 3 mV/°C
Full-scale error DAC register loaded with all '1's ±0.03 ±0.2 % of FSR
Full-scale error drift 2 mV/°C
Zero-code error DAC register loaded with all '0's 1 4 mV
Zero-code error drift 2 mV/°C
Extrapolated from two-point line passing through two
Gain error ±0.01 ±0.15 % of FSR
codes
(2)
, unloaded
ppm of
Gain temperature coefficient ±1
FSR/°C
OUTPUT CHARACTERISTICS
(3)
Output voltage range 0 AV
DD
V
DACs unloaded, 1/4 scale to 3/4 scale 7 ms
Output voltage settling time
R
L
= 1MΩ and C
L
= 470pF 12 ms
Slew rate 0.75 V/ms
R
L
= ∞ 470 pF
Capacitive load stability
R
L
= 2kΩ 1000 pF
Code change glitch impulse 1LSB change around major carry 0.15 nV-s
Digital feedthrough SCL toggling 1.5 nV-s
Power-on glitch R
L
= ∞ 3 mV
Channel-to-channel dc crosstalk Full-scale swing on adjacent channel 0.1 LSB
DC output impedance At midscale input 4.5 Ω
Short-circuit current DAC outputs shorted to GND 25 mA
Power-up time (including settling time) Coming out of power-down mode, AV
DD
= 5V 50 ms
(1) Linearity calculated using a reduced code range; output unloaded.
(2) 12-bit: 30 and 4050; 10-bit: 12 and 1012; 8-bit: 4 and 250
(3) Specified by design or characterization; not production tested.
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