Datasheet

NotAcknowledge
Acknowledge
1 2 8 9
ClockPulsefor
Acknowledgement
S
START
Condition
DataOutput
byTransmitter
DataOutput
byReceiver
SCLfrom
Master
Start
Condition
SDA
Stop
Condition
SDA
SCL
S P
SCL
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010 www.ti.com
TWO-WIRE, I
2
C-COMPATIBLE INTERFACE Other than specific timing signals, the I
2
C interface
works with serial bytes. At the end of each byte, a
The two-wire serial interface used by the DACx578 is
ninth clock cycle is used to generate/detect an
I
2
C-compatible (refer to the I
2
C Bus Specification).
acknowledge signal, as shown in Figure 114. An
The bus consists of a data line (SDA) and a clock line
acknowledge is when the SDA line is pulled low
(SCL) with pull-up resistors. When the bus is idle,
during the high period of the ninth clock cycle. A
both SDA and SCL lines are pulled high. All
not-acknowledge is when the SDA line is left high
I
2
C-compatible devices connect to the I
2
C bus
during the high period of the ninth clock cycle.
through open-drain I/O pins SDA and SCL.
The I
2
C specification states that the device that
controls communication is called a master, and the
devices that are controlled by the master are called
slaves. The master device generates the SCL signal.
The master device also generates special timing
conditions (start, repeated start, and stop) on the bus
to indicate the start or stop of a data transfer, as
shown in Figure 113. Device addressing is also
performed by the master. The master device on an
I
2
C bus is usually a microcontroller or a digital signal
Figure 114. Acknowledge and Not Acknowledge
processor (DSP). The DACx578 operates as a slave
Signals on the I
2
C Bus
device on the I
2
C bus. A slave device acknowledges
the master commands, and upon the direction of the
F/S Mode Protocol
master, either receives or transmits data.
• The master initiates data transfer by generating a
start condition, defined as when a high-to-low
transition occurs on the SDA line while SCL is
high, as shown in Figure 114. All I
2
C-compatible
devices recognize a start condition.
• The master then generates the SCL pulses, and
transmits the 7-bit address and the read/write
direction bit (R/W) on the SDA line. During all
Figure 113.
transmissions, the master ensures that data are
valid. A valid data condition requires the SDA line
Although the DACx578 normally operates as a slave
to be stable during the entire high period of the
receiver, when a master device acquires the
clock pulse, as shown in Figure 115. All devices
DACx578 internal register data, the DACx578 also
recognize the address sent by the master and
operates as a slave transmitter. In this case, the
compare it to the internal fixed addresses. Only
master device reads from the DACx578 (the slave
the slave device with a matching address
transmitter). According to I
2
C terminology, read and
generates an acknowledge by pulling the SDA line
write operations are always performed with respect to
low during the entire high period of the ninth SCL
the master device.
cycle, as shown in Figure 114. Upon detecting this
acknowledge, the master recognizes the
The DACx578 supports the following data transfer
communication link with a slave has been
modes, as defined in the I
2
C Bus Specification:
established.
• Standard mode (100kbps)
• The master generates additional SCL cycles to
• Fast mode (400kbps)
either transmit data to the slave (R/W bit = '0') or
• Fast mode plus (1.0Mbps)
(1)
receive data from the slave (R/W bit = '1'). In
• High-Speed mode (3.4Mbps)
either case, the receiver must acknowledge the
data sent by the transmitter. So the acknowledge
The data transfer protocols for Standard and Fast
signal can either be generated by the master or by
modes are exactly the same; therefore, these modes
the slave, depending on which one is the receiver.
are referred to as F/S mode in this document. The
The 9-bit valid data sequences, consisting of eight
protocol for High-Speed mode is different from the
data bits and one acknowledge bit, can continue
F/S mode, and it is referred to as HS mode. The
as long as necessary.
DACx578 supports 7-bit addressing. Note that 10-bit
• To signal the end of the data transfer, the master
addressing and a general call address are not
generates a stop condition by pulling the SDA line
supported.
from low to high while the SCL line is high (see
Figure 115). This action releases the bus and
(1) The DACx578 supports Fast mode plus speed and timing
specifications only. These devices cannot support the 20mA
stops the communication link with the addressed
low-level output current specification.
28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578