Datasheet

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CROSSTALK
OUTPUT VOLTAGE STABILITY
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
DAC6574
SLAS408 DECEMBER 2003
The DAC6574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.01 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated at
one channel, and measured at the remaining output channel) is typically under -100 dB.
The DAC6574 exhibits excellent temperature stability of ±3 ppm/ °C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a ±25 µV window
for a ±1 °C ambient temperature change. Combined with good dc noise performance and true 10-bit differential
linearity, the DAC6574 becomes a perfect choice for closed-loop control applications.
Settling time to within the 10-bit accurate range of the DAC6574 is achievable within 7 µs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The
high-speed serial interface of the DAC6574 is designed in order to support up to 188 kSPS update rate. For
full-scale output swings, the output stage of each DAC6574 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 µV) given that the code-to-code transition does not cross an Nx64 code boundary. Due to internal
segmentation of the DAC6574, code-to-code glitches occur at each crossing of an Nx64 code boundary. These
glitches can approach 100 mVs for N = 15, but settle out within ~2 µs. Sufficient bypass capacitance is required
to ensure 7 µs settling under capacitive loading. To observe the settling performance under resistive load
conditions, the power supply (hence DAC6574 reference supply) must settle quicker than the DAC6574.
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