Datasheet

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Master Transmitter Writing to a Slave Receiver (DAC6574) in Standard/Fast Modes

DAC6574

SLAS408 – DECEMBER 2003

All write access sequences begin with the device address (with R/ W = 0) followed by the control byte. This

control byte specifies the operation mode of DAC6574 and determines which channel of DAC6574 is being

accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the

following data is power-down data or regular data.

With (PD0-Bit = 0) the DAC6574 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE –

HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I

C-Bus is

recognized (refer to the DATA INPUT MODE section of Table 4 ).

With (PD0-Bit = 1) the DAC6574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN

MODE section of Table 4 ).

Table 4. Write Sequence in F/S Mode

DATA INPUT MODE

Transmitter MSB 6 5 4 3 2 1 LSB Comment

Master Start Begin sequence

Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)

DAC6574 DAC6574 Acknowledges

Master 0 0 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)

DAC6574 DAC6574 Acknowledges

Master D9 D8 D7 D6 D5 D4 D3 D2 Writing data word, high byte

DAC6574 DAC6574 Acknowledges

Master D1 D0 x x x x x x Writing data word, low byte

DAC6574 DAC6574 Acknowledges

Master Data or Stop or Repeated Start

(1)

Data or done

(2)

POWER DOWN MODE

Transmitter MSB 6 5 4 3 2 1 LSB Comment

Master Start Begin sequence

Master 1 0 0 1 1 A1 A0 R/ W Write addressing (R/ W=0)

DAC6574 DAC6574 Acknowledges

Master 0 0 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0 = 1)

DAC6574 DAC6574 Acknowledges

Master PD1 PD2 0 0 0 0 0 0 Writing data word, high byte

DAC6574 DAC6574 Acknowledges

Master 0 0 x x x x x x Writing data word, low byte

DAC6574 DAC6574 Acknowledges

Master Stop or Repeated Start

(1)

Done

(1) Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.

(2) Once DAC6574 is properly addressed and control byte is sent, HIGH–BYTE–LOW–BYTE sequences can repeat until a STOP condition

or repeated START condition is received.