Datasheet

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Control Byte
DAC6573
SLAS402 NOVEMBER 2003
MSB LSB
A3 A2 L1 L0 X Sel1 Sel0 PD0
Table 1. Control Register Bit Descriptions
Bit Name Bit Number/Description
A3 Extended address bit
The state of these bits must match the state of pins A3 and A2 in order for a proper
DAC6573 data update, except in broadcast update mode.
A2 Extended address bit
L1 Load1 (mode select) bit
Are used for selecting the update mode.
L2 Load0 (mode select) bit
00 Store I
2
C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the
temporary register of a selected channel. This mode does not change the DAC output of the selected
channel.
01 Update selected DAC with I
2
C data. Most commonly utilized mode. The contents of MS-BYTE and
LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of the
selected channel. This mode changes the DAC output of the selected channel with the new data.
10 4-channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information) are
stored in the temporary register and in the DAC register of the selected channel. Simultaneously, the
other three channels get updated with previously stored data from the temporary register. This mode
updates all four channels together.
11 Broadcast update mode. This mode has two functions. In broadcast mode, DAC6573 responds
regardless of local address matching, and channel selection becomes irrelevant as all channels update.
This mode is intended to enable up to 64 channels simultaneous update, if used with the I
2
C broadcast
address (1001 0000).
If Sel1=0 All four channels are updated with the contents of their temporary register data.
If Sel1=1 All four channels are updated with the MS-BYTE and LS-BYTE data or powerdown.
Sel1 Buff Sel1 Bit
Channel select bits
Sel0 Buff Sel0 Bit
00 Channel A
01 Channel B
10 Channel C
11 Channel D
PD0 Power Down Flag
0 Normal operation
1 Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2 ).
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