Datasheet

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DAC6573 I
2
C Update Sequence
Address Byte
Broadcast Address Byte
DAC6573
SLAS402 NOVEMBER 2003
The DAC6573 requires a start condition, a valid I
2
C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC6573 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I
2
C address selects the DAC6573. The control byte sets the operational
mode of the selected DAC6573. Once the operational mode is selected by the control byte, DAC6573 expects an
MSB byte followed by an LSB byte for data update to occur. DAC6573 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
The control byte needs not to be resent until a change in operational mode is required. The bits of the control
byte continuously determine the type of update performed. Thus, for the first update, DAC6573 requires a start
condition, a valid I
2
C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC6573 needs an MSB byte, and an LSB byte as long as the control command remains the same.
Using the I
2
C high-speed mode (f
scl
= 3.4 MHz), the clock running at 3.4 MHz, each 10-Bit DAC update other than
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 kSPS. Using the fast mode (f
scl
= 400 kHz), clock running at 400 kHz, maximum DAC update
rate is limited to 22.22 kSPS. Once a stop condition is received, DAC6573 releases the I
2
C bus and awaits a
new start condition.
MSB LSB
1 0 0 1 1 A1 A0 R/ W
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to V
DD
or digital GND, or can be actively driven by
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC6573. Up to 16 devices (DAC6573) can still be connected to the same I
2
C-bus.
MSB LSB
1 0 0 1 0 0 0 0
Broadcast addressing is also supported by DAC6573. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC6573 devices. DAC6573 is designed to work with other members of the
DAC857x, DAC757x, and DAC557x families to support multichannel synchronous update. Using the broadcast
address, DAC6573 responds regardless of the states of the address pins. Broadcast is supported only in write
mode (master writes to DAC6573).
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