Datasheet

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DAC6571 I
2
C Update Sequence
Address Byte
Broadcast Address Byte
Control - Most Significant Byte
Least Significant Byte
DAC6571
SLAS406B – DECEMBER 2003 – REVISED AUGUST 2005
THEORY OF OPERATION (continued)
The DAC6571 requires a start condition, a valid I
2
C address, a control-MSB byte, and an LSB byte for a single
update. After the receipt of each byte, the DAC6571 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I
2
C address selects the DAC6571. The CTRL/MSB byte sets the
operational mode of the DAC6571, and the four most significant bits. The DAC6571 then receives the LSB byte
containing six least significant data bits. The DAC6571 performs an update on the falling edge of the
acknowledge signal that follows the LSB byte.
For the first update, the DAC6571 requires a start condition, a valid I
2
C address, a CTRL/MSB byte, and an LSB
byte. For all consecutive updates, the device needs a CTRL/MSB byte, and an LSB byte.
Using the I
2
C high-speed mode (f
scl
= 3.4 MHz), with the clock running at 3.4 MHz, each 10-bit DAC update other
than the first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte,
acknowledge signal), at 188.88 kSPS. Using the fast mode (f
scl
= 400 kHz), and the clock running at 400 kHz,
the maximum DAC update rate is limited to 22.22 kSPS. Once a stop condition is received, DAC6571 releases
the I
2
C bus and awaits a new start condition.
MSB LSB
1 0 0 1 1 0 A0 0
The address byte is the first byte received following the START condition from the master device. The first six
bits (MSBs) of the address are factory-preset to 100110. The next bit of the address is the device select bit A0.
The A0 address input can be connected to V
DD
or digital GND, or can be actively driven by TTL/CMOS logic
levels. The device address is set by the state of this pin during the power-up sequence of the DAC6571. Up to
two devices (DAC6571) can be connected to the same I
2
C-bus without requiring additional glue logic.
MSB LSB
1 0 0 1 0 0 0 0
Broadcast addressing is also supported by DAC6571. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC6571 devices. Using the broadcast address, DAC6571 responds
regardless of the state of the address pin A0.
The most significant byte (CTRL/MSB[7:0]) consists of two zeros, two power-down bits, and four most significant
bits of 10-bit unsigned binary D/A conversion data.
The least significant byte (LSB[7:0]) consists of the six least significant bits of the 10-bit unsigned binary D/A
conversion data, followed by two don't care bits. DAC6571 updates at the falling edge of the acknowledge signal
that follows the LSB[0] bit.
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