Datasheet

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Change of Data Allowed
Data Line
Stable;
Data Valid
SDA
SCL
Not Acknowledge
Acknowledge
1 2 8 9
Clock Pulse for
Acknowledgement
S
START
Condition
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK
1 2 3 - 8 9
ACK
Address
R/W
DAC6571
SLAS406B – DECEMBER 2003 – REVISED AUGUST 2005
THEORY OF OPERATION (continued)
Figure 42. Bit Transfer on the I
2
C Bus
Figure 43. Acknowledge on the I
2
C Bus
Figure 44. Bus Protocol
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