Datasheet

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THEORY OF OPERATION
D/A SECTION
_
+Resistor String
Ref+
Ref−
DAC Register
V
OUT
50 k 50 k
V
DD
GND
70 k
V
OUT
 V
DD

D
1024
RESISTOR STRING
V
DD
To Output
Amplifier
R
R R
R
GND
Output Amplifier
I
2
C Interface
DAC6571
SLAS406B – DECEMBER 2003 – REVISED AUGUST 2005
The architecture of the DAC6571 consists of a string DAC followed by an output buffer amplifier. Figure 39
shows a generalized block diagram of the DAC architecture.
Figure 39. R-String DAC Architecture
The input coding to the DAC6571 is unsigned binary, which gives the ideal output voltage as:
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 1023.
The resistor string section is shown in Figure 40 . It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
Figure 40. Typical Resistor String
The output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, which
gives an output range of 0 V to V
DD
. It is capable of driving a load of 2 k Ω in parallel with 1000 pF to GND. The
source and sink capabilities of the output amplifier can be seen in the typical characteristics curves. The slew
rate is 1 V/ µs with a half-scale settling time of 7 µs with the output unloaded.
I
2
C is a two-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I
2
C-compatible devices connect to the I
2
C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The DAC6571 works as a slave and supports the following data transfer modes, as defined in the I
2
C-Bus
12