Datasheet

DAC5668/88/89 Hardware Description www.ti.com
Table 5. Input Data Connector J7 – Data B Bus (continued)
Pin Description Pin Description
6 GND 23 CMOS data bit 11
7 CMOS data bit 3 24 GND
8 GND 25 CMOS data bit 12
9 CMOS data bit 4 26 GND
10 GND 27 CMOS data bit 13
11 CMOS data bit 5 28 GND
12 GND 29 CMOS data bit 14
13 CMOS data bit 6 30 GND
14 GND 31 CMOS data bit 15 (LSB)
15 CMOS data bit 7 32 GND
16 GND 33 TX_ENABLE
17 CMOS data bit 8 34 GND
4.6 Clock Configuration
The CDCM7005 requires a VCXO or external clock source to derive its output clock signals.
4.6.1 Buffer Mode
The DAC5668/88/89EVM does not come populated with a VCXO and requires an external sine wave
source with a 1-Vrms, 0-V offset on SMA J20. Under this setup, the CDCM7005 operates as a buffer. To
select this mode, the following changes need to be made:
1. JP2 and JP3 need to be set in position 2-3.
2. If a VCXO is installed, it is recommended to disable it by removing jumper J1.
4.6.2 PLL Mode
A VCXO can be installed in U6 to operate the CDCM7005 as a PLL. The following changes need to be
made:
1. JP2 and JP3 need to be in the 1-2 position.
2. Install jumper J1.
3. A frequency reference (internal or external) needs to be provided.
4.6.3 DAC Clock Options
In both CDCM7005 configurations, the Y1A/Y1B outputs are used to drive the DAC5668/88/89
CLK2/CLK2C inputs. The DAC5668/88/89 can also be operated in dual-clock mode, in which case a
second clock needs to be provided to the device. This clock may be single ended (CLK1) or differential
(CLK1/CLK1C). The CDCM7005 Y2A/Y2B outputs may be used to provide this clock. To do this, the
following changes need to be made:
1. If the clock is single ended, connect jumper JP4 in the 1-2 position.
2. If the clock is differential, connect jumpers JP4 and JP5 in the 1-2 position.
As an output, the CLK1 signal provides a clock at the data rate frequency. The data rate clock is used to
drive a buffer and is accessible through SMA connector J21. This signal can be used to clock the data
source to the DAC. To enable this output, the following changes need to be done to the board:
1. Connect jumper JP4 to position 2-3.
2. Jumper J5 /CLKOUT_EN must be in the 1-2 position.
If the device is not in dual-clock mode, the CLK1 pin can be configured as an output. The CLK1C pin can
be configured as a PLL lock indicator. The PLL lock indicator is connected to LED D4 (JP5 must be in
position 2-3). The DAC5689 does not have the internal PLL feature thus the PLL lock indicator is not
functional.
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DAC5668/88/89EVM SLAU241A–June 2008–Revised March 2010
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