Datasheet
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B0040-01
y2
NCO
DAC
I
Q
RF
Processing
TRF3750
GC4116
GC5016
GC5316
DUC
DUC
DAC5687
CDC7005
y2
y2y2
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Figure 76. System Diagram of a Real IF System Using the DAC5687
With the DAC5687 in external clock mode, a low-phase-noise clock for the DAC5687 at the DAC sample rate
would be generated by a VCXO and PLL such as Texas Instruments CDC7005, which can also provide other
system clocks at the VCXO frequency divided by 2
– n
(n = 0 to 4). In this mode, the DAC5687 PLLLOCK pin
output would typically be used to clock the digital upconverter. With the DAC in PLL clock mode, the same input
rate clock would be used for the DAC clock and digital upconverter and the DAC internal PLL/VCO would
generate the DAC sample rate clock. Note that the internal PLL/VCO phase noise may degrade the quality of the
DAC output signal, and also has higher nonharmonic clock-related spurious signals (see the Nonharmonic
Clock-Related Spurious Signals section).
Either DACA or DACB outputs can be used (with the other DAC put into sleep mode) and would typically be
terminated with a transformer (see the Analog Current Outputs section). An IF filter, either LC or SAW, is used to
suppress the DAC Nyquist zone images and other spurious signals before being mixed to RF with a mixer.
An alternative architecture uses the DAC5687 in a dual-channel mode to create a dual-channel system with real
IF input and output. This would be used for narrower signal bandwidth and at the expense of less output
frequency placement flexibility (see Figure 77 ). Frequency upconversion can be accomplished by using the
high-pass filter and CMIX f
DAC
/2 mixing features.
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