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(a) X2 Mode (b) X4L Mode
f
DAC
− MHz
0
10
20
30
40
50
60
70
80
90
0 100 200 300 400 500
Spurious Amplitude − dBc
G032
f
DAC
/2
f
DAC
− MHz
0
10
20
30
40
50
60
70
80
90
100
0 100 200 300 400 500
Spurious Amplitude − dBc
G033
f
DAC
/2
f
DAC
/4
(c) X4 Mode (d) X8 Mode
f
DAC
− MHz
0
10
20
30
40
50
60
70
80
90
100
0 100 200 300 400 500
Spurious Amplitude − dBc
G034
f
DAC
/2
f
DAC
/4
f
DAC
x 3/4
f
DAC
− MHz
0
10
20
30
40
50
60
70
80
90
100
0 100 200 300 400 500
Spurious Amplitude − dBc
G035
f
DAC
/2
f
DAC/
4
f
DAC
x 3/4
f
DAC
/8
f
DAC
x 7/8
DAC5687
SLWS164E FEBRUARY 2005 REVISED SEPTEMBER 2006
Figure 73 and Figure 74 show the typical worst-case spurious signal amplitudes vs f
DAC
for a signal frequency
f
SIG
= 11 × f
DAC
/32 in each mode for PLL on (PLL clock mode) and PLL off (external and dual-clock modes).
Each spurious signal (f
DAC
/2, f
DAC
/4 and f
DAC
/8) has its own curve. The spurious signal amplitudes can then be
adjusted for the exact signal frequency f
SIG
by applying the amplitude adjustment factor shown in Figure 75 . The
amplitude adjustment factor is the same for each spurious signal (f
DAC
/2, f
DAC
/4, and f
DAC
/8) and is normalized for
f
SIG
= 11 × f
DAC
/32.
Figure 73. Clock-Related Spurious Signal Amplitude With PLL Off for f
SIG
= 11 × f
DAC
/ 32
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