Datasheet
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Analog Current Outputs
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
The full-scale output current is set using external resistor R
BIAS
in combination with an on-chip band-gap voltage
reference source (1.2 V) and control amplifier. Current I
BIAS
through resistor R
BIAS
is mirrored internally to provide
a full-scale output current equal to 16 times IBIAS. The full-scale current IOUT
FS
can be adjusted from 20 mA
down to 2 mA.
The relation between IOUT1 and IOUT2 can be expressed as:
IOUT1 = – IOUT
FS
– IOUT2
Current flowing into a node is denoted as – current, and current flowing out of a node as + current. Because the
output stage is a current sink, the current can only flow from AVDD into the IOUT1 and IOUT2 pins. If IOUT2 =
– 5 mA and IOUT
FS
= 20 mA then:
IOUT1 = – 20 – ( – 5) = – 15 mA
The output current flow in each pin driving a resistive load can be expressed as:
IOUT1 = IOUT
FS
× CODE / 65,536
IOUT2 = IOUT
FS
× (65,535 – CODE) / 65,536
where CODE is the decimal representation of the DAC data input word.
For the case where IOUT1 and IOUT2 drive resistor loads R
L
directly, this translates into single-ended voltages
at IOUT1 and IOUT2:
VOUT1 = AVDD – | IOUT1 | × R
L
VOUT2 = AVDD – | IOUT2 | × R
L
Assuming that the data is full scale (65,535 in offset binary notation) and R
L
is 25 Ω , the differential voltage
between pins IOUT1 and IOUT2 can be expressed as:
VOUT1 = AVDD – | – 20 mA | × 25 Ω = 2.8 V
VOUT2 = AVDD – | – 0 mA | × 25 Ω = 3.3 V
VDIFF = VOUT1 – VOUT2 – 0.5 V
Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would
lead to increased signal distortion.
Figure 59 shows a simplified schematic of the current source array output with corresponding switches.
Differential switches direct the current of each individual NMOS current source to either the positive output node
IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of
the current sources and differential switches, and is typically >300 k Ω in parallel with an output capacitance of
5 pF.
The external output resistors are referred to AVDD. The minimum output compliance at nodes IOUT1 and IOUT2
is limited to AVDD – 0.5 V. The maximum output compliance voltage at nodes IOUT1 and IOUT2 equals AVDD +
0.5 V. Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the DAC5687 device.
Exceeding the minimum output compliance voltage adversely affects distortion performance and integral
nonlinearity. The optimum distortion performance for a single-ended or differential output is achieved when the
maximum full-scale signal at IOUT1 and IOUT2 is in the range of AVDD ± 0.5 V.
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