Datasheet
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T0155-01
PHSTR
clk_in
clk_out
phstratFIFO
Output
clk_cmix
Sequencer
fs/2
OnlyMustBeHighforOneclk_inPeriod
InputDelayLine+FIFODelay
0 180
90
0 180
0 18090 270 0
Sequencer
fs/4
Sequencer
Reset
Input Clock Synchronization of Multiple DAC5687s
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Figure 57. CMIX Reset Synchronization Timing
In addition to the reset function provided by the PHSTR signal, the phstr_del(1:0) bits in register ATEST allow
the user to select the initial (reset) state. Changing the cm_mode lower 2 bits produces the same phase shift
results.
Table 14. Initial State of CMIX After Reset
Fix Mix Selection phstr_del(1:0) Initial State at PHSTR
f
S
/2 00 and 10 Normal
f
S
/2 01 and 11 180-degree shift
f
S
/4 00 Normal
f
S
/4 01 90-degree shift
f
S
/4 10 180-degree shift
f
S
/4 11 270-degree shift
For applications where multiple DAC5687 chips are used, clock synchronization is best achieved by using
dual-clock mode with the FIFO disabled or the PLL-clock mode. In the dual-clock mode with FIFO disabled, an
appropriate clock PLL such as the CDC7005 is required to provide the DAC and input rate clocks that meet the
skew requirement t
align
(see Figure 47 ). An example for synchronizing multiple DAC5687 devices in dual clock
mode with two CDC7005s is shown in Figure 58 . When using the internal PLL-clock mode, synchronization of
multiple using PHSTR is completely deterministic due to the phase/frequency detector in the PLL feedback loop.
All chips using the same CLK1/CLK1C input clock have identical internal clocking phases.
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