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Coarse Mixer (CMIX) Synchronization
B0169-01
PHSTR
PLLLOCK
MUX
CLK1
CLK1C
{PLLVDD,inv_plllock,dual_clk}
clk_in
Clock
Generator
CLK2
CLK2C
clk_out
FIFO
PHSTRSyncto
CoarseMixer
PLL VCO
clk_cmix
Sequencer
Reset
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
sync_cm
DAC5687
SLWS164E FEBRUARY 2005 REVISED SEPTEMBER 2006
The coarse mixer implements the f
DAC
/2 and f
DAC
/4 (and f
DAC
/4) fixed complex mixing operation using simple
complements of the data-path signals to create the proper sequences. The sequences are controlled using a
simple counter, and this counter can be synchronously reset using the PHSTR signal.
Similar to the NCO, the PHSTR signal used by the coarse mixer is from the FIFO output. This introduces the
same uncertainty effect due to the FIFO input-to-output pointer relationship. Bypassing the FIFO and using the
dual external clock mode without FIFO eliminates this uncertainty for systems using multiple DAC5687 devices
when this cannot be tolerated. Using the internal PLL, as with the NCO, allows the complete control and
synchronization of the coarse mixer.
Figure 56. Logic Path for PHSTR Synchronization Signal to CMIX Reset
To enable the PHSTR synchronous reset, the serial interface bit sync_cm in register SYNC_CNTL must be set.
The coarse mixer sequence counter is held in reset when PHSTR is low and operates when PHSTR is high.
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