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PHSTR
Q
D
QFLAG
TXENABLE
DB[15]
DA[15]
Q
D
PLLLOCK
MUX
CLK1
CLK1C
clk_in
MUX
D
PLL VCO
clk_out
sync
sync_fifo(2:0)
1
000
001
010
011
100
101
110
111
Q
resync_fifo_in
CLK2
CLK2C
B0167-01
resync_fifo_out
1
0
Q
D
Q
D
Q
D
Q
D
D
Q
D
Q D Q
D Q
D
Q
D
Q
D
Q
D Q
Clock
Generator
{PLLVDD,inv_plllock,dual_clk}
sync_fifo= “100”
DA[15]FirstRisingEdge
DAC5687
SLWS164E FEBRUARY 2005 REVISED SEPTEMBER 2006
Initialization of the FIFO block involves selecting and asserting a synchronization source. Initialization causes the
input and output pointers to be forced to an offset of 2; the input pointer is forced to the in_sel_a state, while the
output pointer is forced to the sel_q_c state. This initialization of the input and output pointers can cause
discontinuities in a data stream and should therefore be handled at startup.
Table 12. Synchronization Source Selection
sync_fifo(2:0) Synchronization Source
000 TXENABLE pin
001 PHSTR pin
010 QFLAG pin
011 DB[15]
100 DA[15] first transition (one shot)
101 Sync now with SIF write (always on)
110 Sync source disabled (always off)
111 Sync now with SIF write (always on)
All possible sync sources are registered with clk_in and then passed through a synchronous rising edge detector.
Figure 53. DAC5687 FIFO Synchronization Source Logic
For example, if TXENABLE is selected as the sync source, a low-to-high transition on the TXENABLE pin causes
the pointers to be initialized.
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