Datasheet

www.ti.com
IOUTB1
IOUTB2
IOUTA1
IOUTA2
16-Bit
DAC
2f
DATA
2 – 16 y f
DATA
f
DATA
y2
16-Bit
DAC
2f
DATA
y2
FIR1
Edge Triggered
Input Latches
• • •
• • •
DA[15:0]
DEMUX
B0025-02
DA[15:0]
t
s(DATA)
t
h(DATA)
A
0
B
0
A
1
A
N
B
N
B
1
TXENABLE
t
s(TXENABLE)
CLK1 or
PLLLOCK
T0041-01
DA[15:0]
t
s(DATA)
t
h(DATA)
A
0
B
0
A
1
A
N
B
N
B
1
QFLAG
CLK1 or
PLLLOCK
T0001-01
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Figure 49. Interleave Bus Mode Data Path
Figure 50. Interleave Bus Mode Timing Diagram Using TXENABLE
Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels
A and B can be synchronized using either the QFLAG pin or the TXENABLE pin. When qflag in register
config_usb is 0, transitions on TXENABLE identify the interleaved data sequence. The first data after the rising
edge of TXENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed
to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an output
to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 51 ).
Figure 51. Interleave Bus Mode Timing Diagram Using QFLAG
44 Submit Documentation Feedback Copyright © 2005 – 2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687